Jobs at Mythic AI

The Senior RTL Design Engineer will design and implement components for next-generation AI processors, collaborating with various engineering teams to ensure performance and correctness while focusing on low-power, high-performance designs.

Lead DFT implementation and verification for ASIC/SoC designs, focusing on methodologies like MBIST, IJTAG, Scan, and ATPG while collaborating with cross-functional teams.

The role involves optimizing analog-aware software for neural networks, designing algorithms, improving software quality, and collaborating on hardware validation. Requires experience with complex algorithms and communication skills.

The Compiler Engineer will design compiler IRs and strategies for complex algorithmic workloads, collaborating with hardware engineers to enhance ISA and execution models, ensuring performance and correctness, while simplifying developer experiences.

Design Verification Engineers will develop and verify designs for AI processors, collaborating across teams to ensure functionality through rigorous testing and innovative strategies.

Manage complex executive calendars, coordinate travel, handle communications, oversee daily office logistics, and support technology needs.

Develop the next generation AI compiler for Mythic's analog compute, optimizing for dataflow architectures and collaborating with hardware engineers.

Architect and build MLIR ecosystems, extending dialects while ensuring conversion paths. Collaborate with hardware engineers to integrate with PyTorch and modern frameworks.

The role involves implementing DFT features on Mythic's SoCs, contributing to methodology development, and collaborating with design teams throughout the design cycle.

Seeking a Senior Analog Mixed-Signal Design Engineer to work on complex systems, involving low-level SPICE simulations and algorithm development in Python and SystemVerilog. Responsibilities include modeling circuits, tracking specifications, and collaborating across teams.

The Senior Systems Integration Engineer will lead silicon bring-up, debugging, validation, and system characterization, ensuring stable and high-performing hardware platforms across multiple domains.

The Senior Test Engineer will drive production test strategy for AI silicon, focusing on Wafer Sort, Final Package Test, and yield analysis. Responsibilities include developing test programs, collaborating with cross-functional teams, and optimizing test methodologies, ensuring robust manufacturing readiness and quality of silicon products.

The role involves ownership of physical design processes, collaboration in various design areas, mentoring, and optimizing performance, power, and area in advanced nodes.

The Senior Staff Systems Design Engineer will lead the design and development of hardware platforms, ensuring integration between silicon and system design while managing complex PCB designs and collaborating with manufacturing partners.

As a Senior Digital Verification Engineer, you will undertake system and block-level verification, develop test plans, create testbenches and verification infrastructure, and collaborate closely with design teams to ensure the functionality of AI hardware components.

The role involves digital RTL design of SoCs, contributing to architecture and driving methodologies for successful chip designs, while collaborating with various teams.

As a Senior Product Engineer, you will own product engineering execution in silicon manufacturing, drive strategies across characterization and yield learning, and improve product quality and manufacturability through collaboration and data analysis.

The RTL Design Engineer will design and implement components for next-gen AI processors, collaborate on microarchitecture, and drive timing closure, optimizing for performance and power efficiency.

The role involves verifying mixed-signal and digital systems, creating RNMs, ensuring interface clarity, and contributing to methodologies across teams.

Develop and maintain emulation platforms for AI-centric SoCs, integrate RTL, support firmware bring-up, debug co-design issues, and analyze AI workload performance.