Jobs at Mythic AI

Provides full-time, on-site IT infrastructure support for a Bangalore VLSI design center. Responsibilities include Windows, macOS, and Linux endpoint support; identity, access, security, networking, VPN, firewall, server, cloud, remote desktop, and container administration; automation; vendor coordination; and EDA tool support. The role follows global IT standards, coordinates with headquarters, manages infrastructure and security operations, and supports engineering compute environments.

The Senior Test Engineer will drive production test strategy for AI silicon, focusing on Wafer Sort, Final Package Test, and yield analysis. Responsibilities include developing test programs, collaborating with cross-functional teams, and optimizing test methodologies, ensuring robust manufacturing readiness and quality of silicon products.

Lead semiconductor product engineering from silicon bring-up through characterization, yield learning, qualification support, and production ramp. Own product health across wafer sort, package test, and manufacturing correlation; analyze ATE and silicon data; improve screening, quality, manufacturability, automation, and analytics. Partner with design, DFT, test, reliability, quality, manufacturing, OSAT, and foundry teams. The role also validates high-speed interfaces and Functional Safety mechanisms.

Develop and execute reliability and automotive qualification strategies for next-generation AI silicon. Lead stress testing, reliability modeling, failure analysis, and qualification reporting while partnering with design, test, quality, manufacturing, OSATs, foundries, and external labs. Analyze failure data, identify wear-out mechanisms, improve robustness, and balance reliability, cost, schedule, and qualification timelines.

Own day-to-day IT and infrastructure for the Hannover engineering site, including user support, endpoints, servers, networking, storage, corporate applications, licenses, backups, and security standards. Administer Linux, Windows, and macOS environments; support engineering tools, repositories, CI systems, and license servers; manage vendors and assets; and lead migration and integration workstreams to Mythic’s global platforms. Serve as the local escalation point while coordinating closely with global IT and DevOps teams.

Leads corporate IT and DevOps across four international sites, managing teams, SaaS applications, identity, endpoints, networking, datacenter and EDA infrastructure. Owns security, compliance, Linux systems, Kubernetes, CI/CD, developer tooling, physical IT, vendors, budgets and infrastructure modernization. Drives identity automation, OS migrations, SaaS governance, audit readiness, datacenter expansion, international integration and support for semiconductor engineering environments.

Own the rack-level reference architecture for dense AI compute platforms, covering board and chassis design, interconnect topology, power delivery, thermal management, mechanical constraints, and serviceability. Collaborate with software teams on LLM partitioning and fabric requirements, build quantitative performance and system models, lead trade studies, and carry designs through ODM or OEM production and customer deployment.

Build and support a robust EDA/CAD environment for IC design teams. Manage PDK, IP, tool, revision-control, licensing, compute-farm, and infrastructure environments. Develop automated EDA flows, scripts, plug-ins, regression systems, and CI/CD pipelines; troubleshoot Linux/Unix, license-server, and tool integration issues; advise leadership on methodology, tooling, and infrastructure upgrades.

Design and deliver complex, manufacturable PCB reference and system platforms for Mythic silicon. Lead schematic design, PCB layout guidance, SI/PI reviews, fabrication documentation, vendor coordination, bring-up, debug, validation, and production handoff, ensuring power, clocking, connector, mechanical, thermal, and manufacturing constraints are met.

Lead end-to-end systems engineering to turn Mythic analog compute chips into validated, customer-ready cards, modules, and platforms. Build and scale validation teams, drive hardware/software co-validation, own test infrastructure and automation, support OEM/hyperscale qualification, and feed field learnings into product and architecture decisions.

Develop and own DSP and algorithm blocks to mitigate analog impairments for analog compute-in-memory: calibration, non-linearity compensation, offset correction, and error estimation. Build Python frameworks and firmware, improve simulation fidelity, correlate silicon and simulation errors, and lead silicon bring-up, characterization, and productization with cross-functional teams.

Lead and build Mythic's marketing function end-to-end: define brand and category narrative, create vertical and product positioning, build demand-generation and sales enablement assets, recruit and scale a full marketing team, and represent the company externally across data center, automotive, robotics, and defense markets.

Own full-cycle recruiting for technical and leadership semiconductor roles. Partner with hiring managers and executives on hiring strategy, compensation, and org design. Source niche passive candidates, manage high-volume confidential and executive searches, drive offers and negotiations, mentor junior recruiters, and improve TA processes and employer branding.

Design and verify complete non-volatile memory (NVM) IP macros and peripheral circuits for product architectures. Optimize NVM architecture for performance and area, develop interfaces with analog compute blocks, run RNM/functional modeling, collaborate on tapeout, silicon debugging, validation, and production qualification.

The Senior Staff Systems Design Engineer will lead the design and development of hardware platforms, ensuring integration between silicon and system design while managing complex PCB designs and collaborating with manufacturing partners.

Develop and verify designs for AI processors, focusing on system-level verification, testbench development, and collaboration with RTL designers.

The role involves digital RTL design of SoCs, contributing to architecture and driving methodologies for successful chip designs, while collaborating with various teams.

Architect and build MLIR ecosystems, extending dialects while ensuring conversion paths. Collaborate with hardware engineers to integrate with PyTorch and modern frameworks.

As a Senior Digital Verification Engineer, you will undertake system and block-level verification, develop test plans, create testbenches and verification infrastructure, and collaborate closely with design teams to ensure the functionality of AI hardware components.

The role involves implementing DFT features on Mythic's SoCs, contributing to methodology development, and collaborating with design teams throughout the design cycle.