Teams at Mythic AI

Designs and verifies analog and mixed-signal circuits for AI hardware, from SPICE simulations through top-level algorithm modeling in Python and SystemVerilog. Owns interface specifications, cross-functional co-verification, calibration and test algorithms, and chip-level concerns including EM/IR, ESD, and power distribution. Relevant work includes ADC/DAC, PLL, SERDES, sensing, digital controllers, and high-reliability or automotive systems.

Design and verify complete non-volatile memory (NVM) IP macros and peripheral circuits for product architectures. Optimize NVM architecture for performance and area, develop interfaces with analog compute blocks, run RNM/functional modeling, collaborate on tapeout, silicon debugging, validation, and production qualification.

Owns end-to-end semiconductor production test across wafer sort, final package test, characterization, screening, volume ramp, and manufacturing release. Develops and debugs ATE test programs, translates test patterns, analyzes yield and quality data, drives root-cause resolution, and collaborates with design, DFT, product, reliability, manufacturing, OSATs, foundries, and ATE vendors. The role also builds test infrastructure, automation, analytics, and scalable test methodologies for analog and digital AI inference silicon.