Teams at Greenwave Radios

Lead design verification for 5G Open RAN SoC products, covering ARM Cortex subsystems, packet-processing blocks, and high-speed interfaces. Develop SystemVerilog/UVM testbenches, Python/C++ reference-model integrations, constrained-random tests, assertions, coverage, regressions, and hardware/software co-verification environments. Collaborate with architects, RTL, firmware, and systems teams while supporting emulation and FPGA prototyping. Drive verification planning, debugging, coverage closure, and transition of verification scenarios into firmware validation flows.

Senior design verification engineer responsible for verifying wireless DSP hardware blocks and 5G SoC designs. Develops UVM and SystemVerilog testbenches, integrates MATLAB and Python reference models, performs HW/SW co-verification, and executes directed and constrained-random testing. Responsibilities include coverage closure, assertions, regression analysis, debugging, verification planning, emulation, FPGA prototyping, and automated verification flows using scripting languages.

Six-month contract role developing and testing bare-metal and RTOS firmware for 5G SoCs, including device drivers and lower PHY software. Responsibilities include simulation and hardware testing, debugging, architecture and code reviews, documentation, requirements collaboration, and technical mentorship. Requires embedded C/C++, ARM SoC experience, RTOS expertise, unit testing, mocking, build systems, register-level programming, interrupts, DMA, concurrency, and boot/runtime initialization testing.