InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.
Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation.
To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website.
- You will be working within DV team on verifying HW wireless DSP blocks using internal developed reference MATLAB/Python Model.
- Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate.
- Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs.
- Develop and execute verification plans based on design specifications and collaboration with architects and designers.
- Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases.
- Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification.
- Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.
- Assist in emulation, FPGA, prototyping efforts.
- Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts.
- Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS.
- 5 or more years of experience in DSP blocks(FFT, FIR, IIR, AGC, Interpolation/Decimation Filters, Up/Down Converter) design verification using reference models.
- Hands-on experiences in integrating MATLAB/Python models to UVM environment and create Agents, Scoreboards components for DSP blocks.
- Knowledge of wireless communication theories (SNR, IQ constellations, FFT, OFDM, MIMO)
- Experiences in Cadence vManager for DV metrics extraction and regression
- Good understanding of the complete verification life cycle (test plan, testbench through coverage closure).
- Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch.
- Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell.
- Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based
- Experiences in GIT, JIRA, MS office suites
- Competitive salary and stock options.
- Learning and development opportunities.
- Employer paid health Insurance.
- Earned, Casual, Sick & parental leaves.
Skills Required
- Bachelor’s or master’s degree in Electrical, Electronics and Communication, Computer Science, or equivalent engineering discipline
- 5 or more years of experience verifying DSP blocks such as FFT, FIR, IIR, AGC, interpolation/decimation filters, and up/down converters using reference models
- Hands-on experience integrating MATLAB or Python models into UVM environments
- Experience creating UVM agents and scoreboard components for DSP blocks
- Knowledge of wireless communication theory, including SNR, IQ constellations, FFT, OFDM, and MIMO
- Experience using Cadence vManager for design verification metrics extraction and regression
- Understanding of the complete verification lifecycle from test planning through coverage closure
- Expertise developing verification environments and components including monitors, scoreboards, drivers, and agents
- Proficiency in SystemVerilog, Verilog, UVM, and C
- Proficiency with Python, Perl, and Tcl/Shell scripting
- Experience developing IP, subsystem, or chip-level SystemVerilog and UVM-based verification
- Experience with Git, Jira, and Microsoft Office suites
What We Do
InnoPhase Inc., DBA GreenWave™ Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers, spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology.
