Jobs at EnCharge AI

Lead block-level physical implementation from synthesis and floorplan through CTS, routing, and sign-off. Optimize PPA via deep timing, power, and congestion analysis, automate flows with Tcl/Python, resolve DRC/LVS/IR/timing issues, and collaborate with RTL/DFT teams to left-shift constraints and ensure clean GDSII tape-outs.

Lead full RTL-to-GDSII physical design for sub-5nm SoCs: own full flow, optimize PPA, build scalable push-button methodology, remove execution bottlenecks, and collaborate with RTL/Architecture/DFT/foundry/EDA teams.

Conduct hardware-aware ML research and engineering to accelerate AI inference. Build fine-tuning and post-training pipelines, benchmarking and profiling tools, and collaborate with hardware, compiler, and quantization teams to optimize model quality, latency, throughput, and power on novel silicon.

Lead and define end-to-end DFT architecture for complex SoCs, including scan insertion, ATPG, MBIST, IJTAG and boundary scan. Drive edge-specific IST/POST strategies, collaborate across design, PD, and yield teams, and lead post-silicon bring-up and ATE debug to ensure manufacturability and reliability.

Lead development and ownership of full-chip STA sign-off methodology and timing convergence strategy. Architect and deploy STA/ECO flows, benchmark EDA tools (Cadence Tempus), build automation (Tcl/Python/Perl), define MMMC and margin strategies, and collaborate with RTL, CAD, DFT, and Physical Design to meet PPA and tape-out goals.

The Staff DFT Engineer at EnCharge AI will define and implement the DFT architecture for AI accelerators, manage DFT constraints, generate test patterns, and optimize for Edge AI applications while collaborating with ATE teams for silicon debugging.

Develop and optimize AI models for efficient inference on custom silicon. Build fine-tuning pipelines, implement acceleration techniques (quantization, sparsity, distillation), create benchmarking and profiling tools, and collaborate with hardware, compiler, and quantization teams to translate algorithmic improvements into real hardware gains.

The Senior Emulation Engineer will validate AI accelerator architectures, maintain emulation platforms, develop testbenches, and collaborate on performance optimization and debugging processes.

Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.

Own top-level physical integration and signoff for very large SoCs from floorplan to tapeout. Architect hierarchical physical verification flows, execute full-chip DRC/LVS/ERC/antenna/ESD/latch-up signoff, resolve integration bottlenecks with PD/STA, collaborate with foundries on rule co-optimization, and automate PV/integration flows to accelerate tapeout.

Lead floorplanning and PDN design for complex SoCs, optimizing performance targets and power integrity while establishing best practices.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

The LLM Inference Deployment Engineer will deploy and scale large language models efficiently on AI accelerators, focusing on model optimization and low-latency inference.

The Senior NPU Architect will design and optimize architecture modules for AI accelerators, collaborating with teams to enhance performance for AI/ML workloads.

Lead development and optimization of a highly automated RTL-to-GDSII and timing signoff flow. Own Innovus methodology and Tempus STA integration, reduce turnaround time with Python/Tcl automation, interface with Cadence, debug tool/database issues, and mentor PD and timing teams to ensure robust, high-performance physical implementation for AI accelerators.

Seeking a Senior Physical Design Engineer with expertise in chip-level implementation, EDA tools, and low-power design to enhance AI hardware capabilities.

Design and implement graph compiler optimizations (fusion, quantization, tiling) to convert TensorFlow/PyTorch models into IR, improve performance and hardware utilization, collaborate with ML researchers and hardware architects, and lead a team focused on compiler and code-generation improvements.

Lead design and implementation of graph compiler optimizations to convert TensorFlow/PyTorch models into IR, improve performance via fusion, quantization, and tiling, collaborate with hardware and ML teams, and mentor engineers to enable efficient deployment on EnCharge inference accelerators.