Jobs at EnCharge AI

The LLM Inference Deployment Engineer will deploy and scale large language models efficiently on AI accelerators, focusing on model optimization and low-latency inference.

The Senior NPU Architect will design and optimize architecture modules for AI accelerators, collaborating with teams to enhance performance for AI/ML workloads.

Seeking a Senior Physical Design Engineer with expertise in chip-level implementation, EDA tools, and low-power design to enhance AI hardware capabilities.

Design and implement graph compiler optimizations (fusion, quantization, tiling) to convert TensorFlow/PyTorch models into IR, improve performance and hardware utilization, collaborate with ML researchers and hardware architects, and lead a team focused on compiler and code-generation improvements.

Lead design and implementation of graph compiler optimizations to convert TensorFlow/PyTorch models into IR, improve performance via fusion, quantization, and tiling, collaborate with hardware and ML teams, and mentor engineers to enable efficient deployment on EnCharge inference accelerators.

The role involves architecting production systems for video generation, developing APIs, and establishing production operations to support innovative AI applications.

Lead STA strategy and execution for advanced-node SoC/IP designs, develop novel timing methodologies (MCMM, variation modeling, sign-off margins), act as Cadence Tempus SME, collaborate with RTL/synthesis/physical teams for timing-friendly implementations, and mentor the India team through full-cycle STA to GDS sign-off.

Lead block-level physical implementation from synthesis and floorplan through CTS, routing, and sign-off. Optimize PPA via deep timing, power, and congestion analysis, automate flows with Tcl/Python, resolve DRC/LVS/IR/timing issues, and collaborate with RTL/DFT teams to left-shift constraints and ensure clean GDSII tape-outs.

Lead full RTL-to-GDSII physical design for sub-5nm SoCs: own full flow, optimize PPA, build scalable push-button methodology, remove execution bottlenecks, and collaborate with RTL/Architecture/DFT/foundry/EDA teams.

Lead SOC timing convergence by ensuring high-performance paths to tape-out through cross-functional coordination and advanced analysis of timing issues.

Lead testing strategy for AI accelerators, define DFT architecture, implement testing flows, ensure silicon reliability, and manage cross-functional collaboration.

Lead and define end-to-end DFT architecture for complex SoCs, including scan insertion, ATPG, MBIST, IJTAG and boundary scan. Drive edge-specific IST/POST strategies, collaborate across design, PD, and yield teams, and lead post-silicon bring-up and ATE debug to ensure manufacturability and reliability.

The Staff DFT Engineer at EnCharge AI will define and implement the DFT architecture for AI accelerators, manage DFT constraints, generate test patterns, and optimize for Edge AI applications while collaborating with ATE teams for silicon debugging.

The Senior Emulation Engineer will validate AI accelerator architectures, maintain emulation platforms, develop testbenches, and collaborate on performance optimization and debugging processes.

Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

Lead floorplanning and PDN design for complex SoCs, optimizing performance targets and power integrity while establishing best practices.