Lead and own company IT and DevOps operations, manage CPU/GPU compute infrastructure, system and network administration, security practices, vendor relationships, onboarding, and scale-out planning to support hardware and software development teams.

Lead SOC timing convergence by ensuring high-performance paths to tape-out through cross-functional coordination and advanced analysis of timing issues.

Lead testing strategy for AI accelerators, define DFT architecture, implement testing flows, ensure silicon reliability, and manage cross-functional collaboration.

Lead STA strategy and execution for advanced-node SoC/IP designs, develop novel timing methodologies (MCMM, variation modeling, sign-off margins), act as Cadence Tempus SME, collaborate with RTL/synthesis/physical teams for timing-friendly implementations, and mentor the India team through full-cycle STA to GDS sign-off.

Lead block-level physical implementation from synthesis and floorplan through CTS, routing, and sign-off. Optimize PPA via deep timing, power, and congestion analysis, automate flows with Tcl/Python, resolve DRC/LVS/IR/timing issues, and collaborate with RTL/DFT teams to left-shift constraints and ensure clean GDSII tape-outs.

Lead full RTL-to-GDSII physical design for sub-5nm SoCs: own full flow, optimize PPA, build scalable push-button methodology, remove execution bottlenecks, and collaborate with RTL/Architecture/DFT/foundry/EDA teams.

Lead and define end-to-end DFT architecture for complex SoCs, including scan insertion, ATPG, MBIST, IJTAG and boundary scan. Drive edge-specific IST/POST strategies, collaborate across design, PD, and yield teams, and lead post-silicon bring-up and ATE debug to ensure manufacturability and reliability.

The Analog Mixed Signal Design Engineer will develop analog IP and SoCs, design various analog circuits, and oversee test efforts in labs and production.

The Senior Emulation Engineer will validate AI accelerator architectures, maintain emulation platforms, develop testbenches, and collaborate on performance optimization and debugging processes.

Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.

Lead floorplanning and PDN design for complex SoCs, optimizing performance targets and power integrity while establishing best practices.

Seeking a Senior Physical Design Engineer with expertise in chip-level implementation, EDA tools, and low-power design to enhance AI hardware capabilities.