Jobs at EnCharge AI

Leads end-to-end power, performance, and area optimization for AI semiconductor SoCs. Influences architecture, RTL, memory hierarchies, dataflows, floorplanning, multi-voltage domains, synthesis, placement, clock-tree synthesis, routing, and power-analysis workflows. Partners with architecture, RTL, physical design, EDA vendors, and software teams to develop custom methodologies and deliver energy-efficient silicon under stringent PPA constraints.

Lead block-level and top-level physical design for advanced AI semiconductor chips from netlist through foundry tapeout. Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, PPA optimization, power-grid verification, EM/IR resolution, flow automation using Tcl/Python, and collaboration with physical verification and foundry teams.

Own end-to-end embedded software program execution across firmware, drivers, bootloaders, hardware, architecture, compiler, runtime, and validation teams. Align software milestones with tape-out, silicon and board bring-up, validation, and customer delivery. Identify and resolve cross-team risks, manage schedules and operating cadence, support platform enablement, and coordinate distributed engineering teams and external partners for AI accelerator deployments.

Leads customer and partner solution development for AI acceleration platforms, including system design, benchmarking, performance tuning, proof-of-concepts, deployment, technical pre-sales, reference applications, partner enablement, and ecosystem collaboration. Influences product roadmaps while integrating AI hardware, software, systems, and customer workloads for edge, datacenter, and embedded applications.

Lead block-level physical implementation from synthesis and floorplan through CTS, routing, and sign-off. Optimize PPA via deep timing, power, and congestion analysis, automate flows with Tcl/Python, resolve DRC/LVS/IR/timing issues, and collaborate with RTL/DFT teams to left-shift constraints and ensure clean GDSII tape-outs.

Lead full RTL-to-GDSII physical design for sub-5nm SoCs: own full flow, optimize PPA, build scalable push-button methodology, remove execution bottlenecks, and collaborate with RTL/Architecture/DFT/foundry/EDA teams.

Conduct hardware-aware ML research and engineering to accelerate AI inference. Build fine-tuning and post-training pipelines, benchmarking and profiling tools, and collaborate with hardware, compiler, and quantization teams to optimize model quality, latency, throughput, and power on novel silicon.

Lead and define end-to-end DFT architecture for complex SoCs, including scan insertion, ATPG, MBIST, IJTAG and boundary scan. Drive edge-specific IST/POST strategies, collaborate across design, PD, and yield teams, and lead post-silicon bring-up and ATE debug to ensure manufacturability and reliability.

Lead development and ownership of full-chip STA sign-off methodology and timing convergence strategy. Architect and deploy STA/ECO flows, benchmark EDA tools (Cadence Tempus), build automation (Tcl/Python/Perl), define MMMC and margin strategies, and collaborate with RTL, CAD, DFT, and Physical Design to meet PPA and tape-out goals.

Develop and optimize AI models for efficient inference on custom silicon. Build fine-tuning pipelines, implement acceleration techniques (quantization, sparsity, distillation), create benchmarking and profiling tools, and collaborate with hardware, compiler, and quantization teams to translate algorithmic improvements into real hardware gains.

The Senior Emulation Engineer will validate AI accelerator architectures, maintain emulation platforms, develop testbenches, and collaborate on performance optimization and debugging processes.

Lead the DFT architecture and strategy for complex SoCs, overseeing scan/ATPG, MBIST/logic BIST, IJTAG/boundary scan, post-silicon ATE bring-up, and edge-specific IST/POST to ensure manufacturability, reliability, and minimal power/area impact.

Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.

Own top-level physical integration and signoff for very large SoCs from floorplan to tapeout. Architect hierarchical physical verification flows, execute full-chip DRC/LVS/ERC/antenna/ESD/latch-up signoff, resolve integration bottlenecks with PD/STA, collaborate with foundries on rule co-optimization, and automate PV/integration flows to accelerate tapeout.

Lead floorplanning and PDN design for complex SoCs, optimizing performance targets and power integrity while establishing best practices.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

Lead logic synthesis and signoff for blocks and sub-chips, drive synthesis flow and automation, collaborate with RTL engineers to produce synthesis-friendly netlists, optimize timing/levels of logic, and expand into PNR, STA, and full-chip timing convergence.

The Senior NPU Architect will design and optimize architecture modules for AI accelerators, collaborating with teams to enhance performance for AI/ML workloads.

Lead development and optimization of a highly automated RTL-to-GDSII and timing signoff flow. Own Innovus methodology and Tempus STA integration, reduce turnaround time with Python/Tcl automation, interface with Cadence, debug tool/database issues, and mentor PD and timing teams to ensure robust, high-performance physical implementation for AI accelerators.

Lead SoC-level floorplanning from concept to tape-out for large AI/Data Center chips. Collaborate with architects and RTL leads to optimize PPA, manage bump/package co-design, integrate AMS IPs and high-speed SerDes, design top-level PDN and pin assignments, and develop automated floorplanning workflows (Tcl/Python).