Teams at EnCharge AI

Leads end-to-end power, performance, and area optimization for AI semiconductor SoCs. Influences architecture, RTL, memory hierarchies, dataflows, floorplanning, multi-voltage domains, synthesis, placement, clock-tree synthesis, routing, and power-analysis workflows. Partners with architecture, RTL, physical design, EDA vendors, and software teams to develop custom methodologies and deliver energy-efficient silicon under stringent PPA constraints.

Lead block-level and top-level physical design for advanced AI semiconductor chips from netlist through foundry tapeout. Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, PPA optimization, power-grid verification, EM/IR resolution, flow automation using Tcl/Python, and collaboration with physical verification and foundry teams.

Own end-to-end embedded software program execution across firmware, drivers, bootloaders, hardware, architecture, compiler, runtime, and validation teams. Align software milestones with tape-out, silicon and board bring-up, validation, and customer delivery. Identify and resolve cross-team risks, manage schedules and operating cadence, support platform enablement, and coordinate distributed engineering teams and external partners for AI accelerator deployments.