Teams at EnCharge AI

Lead development and ownership of full-chip STA sign-off methodology and timing convergence strategy. Architect and deploy STA/ECO flows, benchmark EDA tools (Cadence Tempus), build automation (Tcl/Python/Perl), define MMMC and margin strategies, and collaborate with RTL, CAD, DFT, and Physical Design to meet PPA and tape-out goals.

The Staff DFT Engineer at EnCharge AI will define and implement the DFT architecture for AI accelerators, manage DFT constraints, generate test patterns, and optimize for Edge AI applications while collaborating with ATE teams for silicon debugging.

Develop and optimize AI models for efficient inference on custom silicon. Build fine-tuning pipelines, implement acceleration techniques (quantization, sparsity, distillation), create benchmarking and profiling tools, and collaborate with hardware, compiler, and quantization teams to translate algorithmic improvements into real hardware gains.