Teams at EnCharge AI

Lead block-level physical implementation from synthesis and floorplan through CTS, routing, and sign-off. Optimize PPA via deep timing, power, and congestion analysis, automate flows with Tcl/Python, resolve DRC/LVS/IR/timing issues, and collaborate with RTL/DFT teams to left-shift constraints and ensure clean GDSII tape-outs.

Lead full RTL-to-GDSII physical design for sub-5nm SoCs: own full flow, optimize PPA, build scalable push-button methodology, remove execution bottlenecks, and collaborate with RTL/Architecture/DFT/foundry/EDA teams.

Conduct hardware-aware ML research and engineering to accelerate AI inference. Build fine-tuning and post-training pipelines, benchmarking and profiling tools, and collaborate with hardware, compiler, and quantization teams to optimize model quality, latency, throughput, and power on novel silicon.