Jobs at Cornelis Networks

Develop product messaging, positioning, and sales enablement for high-performance AI and HPC networking products. Collaborate with engineering, product, and sales to create collateral, conduct market and competitive analysis, engage customers, and shape go-to-market strategies for interconnect technologies.

Develop and run UVM-based verification environments and tests for block, unit, and SoC levels; collect and analyze functional and code coverage; perform formal block-level verification and participate in post-silicon validation of complex SoCs.

Lead and grow the RTL design engineering team to deliver next-generation networking ASICs. Own RTL schedules, coordinate cross-functional execution (DV, emulation, physical design), manage headcount and hiring, mitigate schedule risks, and ensure tape-out readiness while optimizing PPA and subsystem integration.

Lead SoC verification strategy and execution: design UVM/SystemVerilog testbenches, run regressions, drive coverage closure, debug RTL failures, collaborate with design/emulation/silicon teams, and mentor verification engineers to ensure first-pass silicon success.

Develop and maintain SAI and switch SDK components for next-generation ASIC platforms, integrate with NOS like SONiC, build test/CI frameworks, optimize performance, collaborate with hardware and firmware teams, and mentor engineers.

Lead and coordinate software program execution across engineering, test, DevOps, product, and field teams. Drive release planning, cross-functional alignment, risk identification, dashboards and status reporting, customer-impacting issue resolution, and continuous improvement of engineering processes and tooling.

Own strategy and execution for company presence at industry events. Manage event calendar, budgets, booth strategy, vendor coordination, on-site execution, lead capture, cross-functional alignment, and post-event reporting to drive pipeline and brand.

Design and implement advanced Ethernet protocol blocks for next-generation ASICs. Write microarchitecture specifications, define RTL timing constraints, collaborate with physical design and verification teams pre-silicon, and work with hardware/firmware/software teams to diagnose and resolve post-silicon ASIC issues.

Define and drive product strategy and roadmap for high-performance networking targeting AI and HPC datacenters. Partner with customers, OEMs/ODMs, cloud/hyperscalers, and internal architects, silicon and systems engineers to translate workload and system requirements into product requirements, secure design wins, and accelerate adoption. Own business cases, phase-gate reviews, executive communications, and use AI-assisted tools to scale product management impact.

Lead product management for storage ecosystem qualification of Cornelis NICs and switches. Drive technical validation, partner certification, roadmap alignment, GTM activation, and cross-functional coordination with storage providers, sales, and engineering to secure design wins and ensure high-performance end-to-end AI/HPC solutions.

Design and implement RTL (Verilog/SystemVerilog) for high-speed datapaths and packet processing; define timing constraints and support timing closure; collaborate on verification, post-silicon validation, system-level debug, and performance/power optimization for Host Fabric Interface/ethernet subsystems.

Lead NOS platform porting and BSP development for switch ASICs, integrate and validate drivers, hardware monitoring and BMC interfaces, implement control/data plane components for SONiC and FBOSS, build test infrastructure and CI/CD, profile and optimize performance, and collaborate across hardware, firmware, and SAI/SDK teams while engaging with open-source communities.

Perform SI simulations and measurements for high-speed interfaces (PCIe, Ethernet), correlate lab results with models, provide design guidelines, review PCB/platform layouts, and support cross-functional teams through product development to production.

Design and optimize AI communication middleware for distributed multi-node, multi-GPU training. Implement C/C++ performance-critical features, improve GPU communication paths, profile and tune frameworks (PyTorch, TensorFlow, JAX, DeepSpeed), develop benchmarks, contribute upstream, and collaborate with kernel, driver, switch, and systems teams to validate and deploy high-performance networking for AI/HPC.

Lead SOC-level verification strategy and execution for high-performance AI/HPC networking ASICs. Drive UVM/SystemVerilog testbench development, regressions, coverage closure, RTL debug, cross-functional collaboration, and mentor verification teams to ensure first-pass silicon success.

Lead design and implementation of Kubernetes integration for Cornelis Networks' fabric management: build Go-based operators/controllers, extend Kubernetes for specialized hardware and scheduling, enable cloud-native orchestration of fabric services, collaborate across platform and hardware teams, contribute upstream, and document best practices while leveraging AI-assisted development tools.

Lead end-to-end execution of complex networking product programs, coordinating cross-functional teams (ASIC, platform, software, validation, manufacturing) to deliver scalable AI/HPC interconnect solutions on time and within budget. Manage timelines, budgets, risks, reporting, stakeholder reviews, and mentor program managers and engineering leads while promoting agile and lifecycle best practices.

Lead integration and validation of PCIe controllers in SoCs, optimize PCIe stack performance, drive silicon bring-up and lab validation, debug RTL/gate/silicon issues, ensure PCIe compliance, collaborate across IP, verification, physical design and software teams, and mentor junior engineers.