Jobs at Cornelis Networks

The Senior Account Manager will develop and execute sales strategies for HPC and AI networking solutions across higher education and automotive accounts. Responsibilities include prospecting, building customer relationships, managing Salesforce pipeline activity, meeting quotas, collaborating with channel and OEM partners, presenting technical solutions, and providing market feedback. The role requires a self-generating hunter mentality, grant proposal experience, technical knowledge of network interconnects, and up to 50% travel for conferences and customer meetings.

Design and implement RTL (Verilog/SystemVerilog) for high-speed datapaths and packet processing; define timing constraints and support timing closure; collaborate on verification, post-silicon validation, system-level debug, and performance/power optimization for Host Fabric Interface/ethernet subsystems.

Lead SoC verification strategy and execution: design UVM/SystemVerilog testbenches, run regressions, drive coverage closure, debug RTL failures, collaborate with design/emulation/silicon teams, and mentor verification engineers to ensure first-pass silicon success.

Lead integration and validation of PCIe controllers in SoCs, optimize PCIe stack performance, drive silicon bring-up and lab validation, debug RTL/gate/silicon issues, ensure PCIe compliance, collaborate across IP, verification, physical design and software teams, and mentor junior engineers.

Perform SI simulations and measurements for high-speed interfaces (PCIe, Ethernet), correlate lab results with models, provide design guidelines, review PCB/platform layouts, and support cross-functional teams through product development to production.

Design and implement advanced Ethernet protocol blocks for next-generation ASICs. Write microarchitecture specifications, define RTL timing constraints, collaborate with physical design and verification teams pre-silicon, and work with hardware/firmware/software teams to diagnose and resolve post-silicon ASIC issues.

Lead end-to-end execution of complex networking product programs, coordinating cross-functional teams (ASIC, platform, software, validation, manufacturing) to deliver scalable AI/HPC interconnect solutions on time and within budget. Manage timelines, budgets, risks, reporting, stakeholder reviews, and mentor program managers and engineering leads while promoting agile and lifecycle best practices.

Lead design and implementation of Kubernetes integration for Cornelis Networks' fabric management: build Go-based operators/controllers, extend Kubernetes for specialized hardware and scheduling, enable cloud-native orchestration of fabric services, collaborate across platform and hardware teams, contribute upstream, and document best practices while leveraging AI-assisted development tools.

Design and optimize AI communication middleware for distributed multi-node, multi-GPU training. Implement C/C++ performance-critical features, improve GPU communication paths, profile and tune frameworks (PyTorch, TensorFlow, JAX, DeepSpeed), develop benchmarks, contribute upstream, and collaborate with kernel, driver, switch, and systems teams to validate and deploy high-performance networking for AI/HPC.

Develop and maintain SAI and switch SDK components for next-generation ASIC platforms, integrate with NOS like SONiC, build test/CI frameworks, optimize performance, collaborate with hardware and firmware teams, and mentor engineers.

Lead and grow the RTL design engineering team to deliver next-generation networking ASICs. Own RTL schedules, coordinate cross-functional execution (DV, emulation, physical design), manage headcount and hiring, mitigate schedule risks, and ensure tape-out readiness while optimizing PPA and subsystem integration.

Develop product messaging, positioning, and sales enablement for high-performance AI and HPC networking products. Collaborate with engineering, product, and sales to create collateral, conduct market and competitive analysis, engage customers, and shape go-to-market strategies for interconnect technologies.

Lead SOC-level verification strategy and execution for high-performance AI/HPC networking ASICs. Drive UVM/SystemVerilog testbench development, regressions, coverage closure, RTL debug, cross-functional collaboration, and mentor verification teams to ensure first-pass silicon success.

Design, develop, and upstream-enable AI/HPC communication middleware (MPI/SHMEM, NCCL/RCCL). Integrate middleware with transports (libfabric/UCX/verbs), optimize performance, collaborate across kernel/driver and switch teams, analyze performance traces, reproduce and fix customer issues, and contribute to open-source projects.

Develop and optimize AI/HPC communication middleware (MPI/SHMEM, CCL/NCCL/RCCL) over Cornelis interconnects; integrate with transports (libfabric/OFI, UCX), contribute upstream open-source, collaborate across kernel/driver and switch teams, and analyze performance traces to reproduce and fix customer issues.

Design and develop system and PCB architectures from concept through production for high-performance networking platforms. Select components, create schematics and design files, support layout, debug system-level issues, assist software integration, and support testing, compliance, and manufacturing transfer.

Lead platform porting and BSP development for switch ASICs, integrate drivers and hardware (BMC, optics), develop control and data plane components for SONiC and FBOSS, build test frameworks and CI/CD, optimize NOS performance, and collaborate across hardware, firmware, and SDK teams while leveraging AI-assisted tooling.

Lead SAI/SDK development for switch ASIC platforms: design SAI object types/APIs, build low-level ASIC drivers and HAL, integrate with SONiC/NOS, develop test frameworks and CI/CD, profile and optimize performance, and mentor engineers.

Design, build, and maintain Kubernetes operators, controllers, and fabric management software in Go to enable deployment, orchestration, and scaling of high-performance interconnect hardware for AI and HPC clusters. Contribute upstream, create automated end-to-end validation frameworks, collaborate with hardware and platform teams, and author technical documentation and best practices.

Lead mechanical design and architecture for high-performance interconnect products (PCIe adapters, switches). Drive NPI through EVT/DVT to mass production, optimize designs for manufacturability (die cast, sheet metal, extrusion), own CAD/PLM models and BOMs, collaborate with thermal/electrical/manufacturing teams, perform prototyping, tolerance stack-up, and mechanical qualification testing.