Jobs at Cornelis Networks

Design and implement Verilog/SystemVerilog RTL for high-speed ASIC data paths and packet processing. Develop timing constraints, collaborate on verification and physical design, support timing closure, and debug post-silicon issues with hardware, firmware, and software teams. Contribute to power-aware performance optimization for Host Fabric Interface subsystems used in AI and HPC networking.

Develop and maintain AI-based ASIC verification automation flows, regression infrastructure, dashboards, reporting tools, and triage automation. Build scripts and integrations using Python, Perl, Tcl, shell scripting, and Make. Support simulation, coverage, lint, formal, emulation, continuous integration, EDA tool integration, and distributed compute infrastructure. Debug automation, tool, runtime, licensing, queue, and workflow issues while improving verification reliability, reproducibility, and efficiency across geographically distributed engineering teams.

Develop and support hardware and software manufacturing test processes for networking products produced through contract manufacturers. Responsibilities include designing PCB test fixtures, creating functional test procedures, troubleshooting production and RMA failures, supporting NPI transitions, training manufacturing teams, managing test software releases, performing failure analysis, and maintaining test documentation. The role also involves hands-on electronic troubleshooting, assembly rework, prototype support, and collaboration between engineering and manufacturing.

Design and implement advanced Ethernet protocols for next-generation ASICs used in AI and HPC networking. Responsibilities include writing microarchitecture specifications, defining timing constraints, collaborating on timing optimization and verification planning, ensuring design coverage, and debugging post-silicon issues with hardware, firmware, and software teams.

Lead and grow the RTL design engineering team responsible for next-generation networking ASICs. Own RTL delivery schedules, coordinate design verification, emulation, and physical design dependencies, manage timing-closure and tape-out readiness, identify schedule risks, and allocate resources. Develop headcount and organizational plans, lead hiring, and scale globally distributed engineering practices while contributing hands-on expertise in microarchitecture, RTL design, synthesis, verification, and PPA optimization.

Verify RTL for advanced ASICs and SoCs at block, unit, and system-on-chip levels. Develop UVM testbenches, write and execute verification tests, analyze functional and code coverage, perform block-level formal verification, and support post-silicon verification. The role requires validating complex SoCs with multiple clock and reset domains and using scripting languages for verification automation.

Design and implement Verilog/SystemVerilog RTL for high-speed ASIC data paths and packet processing. Collaborate on verification, timing constraints, physical design, post-silicon validation, system debugging, performance optimization, and power-aware Host Fabric Interface designs. The role focuses on Ethernet, networking protocols, high-performance computing, AI interconnects, and SoC development.

Lead end-to-end PCIe IP integration into complex ASIC and SoC designs, collaborating across architecture, verification, physical design, software, and external IP vendors. Optimize PCIe performance, contribute to IO and interconnect architecture, and lead silicon bring-up, interoperability testing, and debugging across RTL, gate-level, emulation, and post-silicon environments. Mentor engineers and establish PCIe subsystem development practices for high-performance AI and HPC platforms.

Leads verification closure for ASIC modules, subsystems, and SoCs used in AI and HPC networking. Defines verification strategies, develops UVM testbenches, executes functional tests, manages regression and coverage closure, debugs RTL issues, and collaborates with design, software, emulation, hardware, and post-silicon teams. Provides technical leadership, mentoring, coding guidance, and promotes AI tools for verification productivity.

Lead verification closure for complex ASICs and SoCs used in AI and high-performance computing networking. Define verification strategies, develop UVM/SystemVerilog testbenches, execute functional testing, debug RTL failures, and close functional and code coverage. Guide block, subsystem, and SoC verification while collaborating with design, software, emulation, hardware, and post-silicon teams. Mentor engineers, establish verification guidelines, and promote AI tools to improve team productivity.

The Senior Account Manager will develop and execute sales strategies for HPC and AI networking solutions across higher education and automotive accounts. Responsibilities include prospecting, building customer relationships, managing Salesforce pipeline activity, meeting quotas, collaborating with channel and OEM partners, presenting technical solutions, and providing market feedback. The role requires a self-generating hunter mentality, grant proposal experience, technical knowledge of network interconnects, and up to 50% travel for conferences and customer meetings.

Perform SI simulations and measurements for high-speed interfaces (PCIe, Ethernet), correlate lab results with models, provide design guidelines, review PCB/platform layouts, and support cross-functional teams through product development to production.

Design and optimize AI communication middleware for distributed multi-node, multi-GPU training. Implement C/C++ performance-critical features, improve GPU communication paths, profile and tune frameworks (PyTorch, TensorFlow, JAX, DeepSpeed), develop benchmarks, contribute upstream, and collaborate with kernel, driver, switch, and systems teams to validate and deploy high-performance networking for AI/HPC.

Design, develop, and upstream-enable AI/HPC communication middleware (MPI/SHMEM, NCCL/RCCL). Integrate middleware with transports (libfabric/UCX/verbs), optimize performance, collaborate across kernel/driver and switch teams, analyze performance traces, reproduce and fix customer issues, and contribute to open-source projects.

Develop and optimize AI/HPC communication middleware (MPI/SHMEM, CCL/NCCL/RCCL) over Cornelis interconnects; integrate with transports (libfabric/OFI, UCX), contribute upstream open-source, collaborate across kernel/driver and switch teams, and analyze performance traces to reproduce and fix customer issues.

Design and develop system and PCB architectures from concept through production for high-performance networking platforms. Select components, create schematics and design files, support layout, debug system-level issues, assist software integration, and support testing, compliance, and manufacturing transfer.

Lead mechanical design and architecture for high-performance interconnect products (PCIe adapters, switches). Drive NPI through EVT/DVT to mass production, optimize designs for manufacturability (die cast, sheet metal, extrusion), own CAD/PLM models and BOMs, collaborate with thermal/electrical/manufacturing teams, perform prototyping, tolerance stack-up, and mechanical qualification testing.

Provide technical support for Cornelis Networks products: own issue diagnosis and resolution, manage customer tickets and on-call rotations, collaborate cross-functionally, support OEMs/system integrators for cluster installs, prepare customers for updates, and advocate for customers through the product lifecycle.

Design, implement, and operate a private, secure AI platform and autonomous agent workforce for engineering workflows. Build agents (FastAPI/CLI/chat), integrate MCP and RAG, maintain containerized infrastructure, CI/CD validation, secrets and cost management, and enterprise integrations (GitHub, Jira, Confluence, Teams). Continuously evaluate models, improve agent reliability, and drive platform adoption across low-level systems engineering domains.