Jobs at Cornelis Networks

Design and develop system and PCB architectures from concept through production for high-performance networking platforms. Select components, create schematics and design files, support layout, debug system-level issues, assist software integration, and support testing, compliance, and manufacturing transfer.

Lead platform porting and BSP development for switch ASICs, integrate drivers and hardware (BMC, optics), develop control and data plane components for SONiC and FBOSS, build test frameworks and CI/CD, optimize NOS performance, and collaborate across hardware, firmware, and SDK teams while leveraging AI-assisted tooling.

Lead SAI/SDK development for switch ASIC platforms: design SAI object types/APIs, build low-level ASIC drivers and HAL, integrate with SONiC/NOS, develop test frameworks and CI/CD, profile and optimize performance, and mentor engineers.

Design, build, and maintain Kubernetes operators, controllers, and fabric management software in Go to enable deployment, orchestration, and scaling of high-performance interconnect hardware for AI and HPC clusters. Contribute upstream, create automated end-to-end validation frameworks, collaborate with hardware and platform teams, and author technical documentation and best practices.

Lead mechanical design and architecture for high-performance interconnect products (PCIe adapters, switches). Drive NPI through EVT/DVT to mass production, optimize designs for manufacturability (die cast, sheet metal, extrusion), own CAD/PLM models and BOMs, collaborate with thermal/electrical/manufacturing teams, perform prototyping, tolerance stack-up, and mechanical qualification testing.

Lead planning and execution of integrated B2B campaigns and ABM programs, own marketing automation and attribution systems, run paid media and webinar programs, align marketing with SDRs and sales/channel partners, and build KPI reporting to connect activity to pipeline and revenue.

Provide technical support for Cornelis Networks products: own issue diagnosis and resolution, manage customer tickets and on-call rotations, collaborate cross-functionally, support OEMs/system integrators for cluster installs, prepare customers for updates, and advocate for customers through the product lifecycle.

Design, validate, and document HPC/AI networking solutions; qualify and close sales opportunities in Japan; deliver technical presentations; author technical materials; gather and align customer requirements; travel to conferences and customer sites to position solutions.

Design, implement, and execute verification environments and tests for ASICs and SoCs using UVM. Instrument testbenches for functional and code coverage, run formal block-level verification, analyze coverage results, and support post-silicon validation to ensure first-pass silicon quality.

Design, implement, and operate a private, secure AI platform and autonomous agent workforce for engineering workflows. Build agents (FastAPI/CLI/chat), integrate MCP and RAG, maintain containerized infrastructure, CI/CD validation, secrets and cost management, and enterprise integrations (GitHub, Jira, Confluence, Teams). Continuously evaluate models, improve agent reliability, and drive platform adoption across low-level systems engineering domains.

Lead post-silicon bring-up, validation, and performance characterization of Ethernet networking silicon. Build and benchmark RoCEv2 fabrics, develop test plans, analyze throughput/latency/congestion, create diagnostic tools, debug customer issues, and provide actionable feedback to silicon, firmware, and system teams to optimize datacenter performance.

Develop product messaging, positioning, and sales enablement for high-performance AI and HPC networking products. Collaborate with engineering, product, and sales to create collateral, conduct market and competitive analysis, engage customers, and shape go-to-market strategies for interconnect technologies.

Lead and grow the RTL design engineering team to deliver next-generation networking ASICs. Own RTL schedules, coordinate cross-functional execution (DV, emulation, physical design), manage headcount and hiring, mitigate schedule risks, and ensure tape-out readiness while optimizing PPA and subsystem integration.

Lead SoC verification strategy and execution: design UVM/SystemVerilog testbenches, run regressions, drive coverage closure, debug RTL failures, collaborate with design/emulation/silicon teams, and mentor verification engineers to ensure first-pass silicon success.

Develop and maintain SAI and switch SDK components for next-generation ASIC platforms, integrate with NOS like SONiC, build test/CI frameworks, optimize performance, collaborate with hardware and firmware teams, and mentor engineers.

Design and implement advanced Ethernet protocol blocks for next-generation ASICs. Write microarchitecture specifications, define RTL timing constraints, collaborate with physical design and verification teams pre-silicon, and work with hardware/firmware/software teams to diagnose and resolve post-silicon ASIC issues.

Define and drive product strategy and roadmap for high-performance networking targeting AI and HPC datacenters. Partner with customers, OEMs/ODMs, cloud/hyperscalers, and internal architects, silicon and systems engineers to translate workload and system requirements into product requirements, secure design wins, and accelerate adoption. Own business cases, phase-gate reviews, executive communications, and use AI-assisted tools to scale product management impact.

Design and implement RTL (Verilog/SystemVerilog) for high-speed datapaths and packet processing; define timing constraints and support timing closure; collaborate on verification, post-silicon validation, system-level debug, and performance/power optimization for Host Fabric Interface/ethernet subsystems.

Lead NOS platform porting and BSP development for switch ASICs, integrate and validate drivers, hardware monitoring and BMC interfaces, implement control/data plane components for SONiC and FBOSS, build test infrastructure and CI/CD, profile and optimize performance, and collaborate across hardware, firmware, and SAI/SDK teams while engaging with open-source communities.

Perform SI simulations and measurements for high-speed interfaces (PCIe, Ethernet), correlate lab results with models, provide design guidelines, review PCB/platform layouts, and support cross-functional teams through product development to production.