Teams at Cornelis Networks

Design and implement advanced Ethernet protocols for next-generation ASICs used in AI and high-performance computing networks. Responsibilities include writing microarchitecture specifications, defining RTL timing constraints, collaborating with physical design and verification engineers on timing optimization and test coverage, and debugging post-silicon issues with hardware, firmware, and software teams.

Optimize distributed AI training and inference across CPU/GPU clusters, networking silicon, and software stacks. Benchmark workloads, tune distributed serving and training architectures, analyze communication and system bottlenecks, validate RDMA and collective performance, and create customer-facing proof points. Use profiling and observability tools to visualize performance, compare interconnects, and communicate best practices through technical documentation, publications, and customer engagements.

Lead verification closure for complex ASICs, SoCs, and networking hardware. Define verification strategies, develop UVM testbenches, create functional tests, debug RTL failures, and close functional and code coverage. Collaborate with design, software, emulation, hardware, and silicon validation teams. Guide and mentor verification engineers while establishing coding and verification standards and applying AI tools to improve team productivity.