Teams at Cornelis Networks

Design and implement Verilog/SystemVerilog RTL for high-speed ASIC data paths and packet processing. Develop timing constraints, collaborate on verification and physical design, support timing closure, and debug post-silicon issues with hardware, firmware, and software teams. Contribute to power-aware performance optimization for Host Fabric Interface subsystems used in AI and HPC networking.

Develop and maintain AI-based ASIC verification automation flows, regression infrastructure, dashboards, reporting tools, and triage automation. Build scripts and integrations using Python, Perl, Tcl, shell scripting, and Make. Support simulation, coverage, lint, formal, emulation, continuous integration, EDA tool integration, and distributed compute infrastructure. Debug automation, tool, runtime, licensing, queue, and workflow issues while improving verification reliability, reproducibility, and efficiency across geographically distributed engineering teams.

Develop and support hardware and software manufacturing test processes for networking products produced through contract manufacturers. Responsibilities include designing PCB test fixtures, creating functional test procedures, troubleshooting production and RMA failures, supporting NPI transitions, training manufacturing teams, managing test software releases, performing failure analysis, and maintaining test documentation. The role also involves hands-on electronic troubleshooting, assembly rework, prototype support, and collaboration between engineering and manufacturing.