Jobs at Cerebras Systems

The Deployment Engineer will manage AI inference clusters, optimizing deployment, capacity allocation, and ensuring reliability of pipeline operations across datacenters.

Lead PCB design from specification through implementation, bring-up, qualification, and production. Own schematics, component selection, and layout. Perform lab bring-up, debugging, and automated benchtop test development. Collaborate with manufacturing, test, supply chain, ASIC, mechanical, signal integrity, power delivery, layout, embedded, and diagnostics teams.

The role involves developing infrastructure for benchmarking AI inference performance, analyzing system behavior, designing telemetry systems, and collaborating with teams to improve feature performance.

The role involves synthesizing, placing, and routing high-speed designs, collaborating with RTL teams, and optimizing designs for power/performance area.

The Senior Performance Analyst will benchmark Cerebras' AI inference performance, analyze competitor pricing, and provide pricing recommendations to enhance the customer value proposition, requiring deep expertise in ML frameworks and architecture.

The Business Operations Lead will partner with senior leaders to manage operations in the Datacenter organization, ensuring alignment and efficient execution of plans and priorities, while improving transparency and decision-making mechanisms.

As a Network Architect, you'll design AI/ML and HPC clusters, address performance bottlenecks, drive multi-team projects, and collaborate with vendors.

Manage AI compute clusters, monitor systems health, optimize resources, and troubleshoot technical issues, ensuring high performance for ML applications.

Develop and maintain the architecture for Cerebras' Inference Cloud Platform, focusing on distributed systems, performance optimization, and technical direction. Responsibilities include coding, design reviews, and mentoring senior engineers.

The Senior Cloud Quality Engineer will ensure the quality of cloud releases, build scalable test infrastructure, and collaborate with various teams to improve testing processes. Exceptional experience in cloud environments, test engineering, and communication is essential.

You will prototype and benchmark model innovations, develop automation for experiments, and work with teams on software/hardware integration.

As an ASIC Architect at Cerebras Systems, you will translate high-level architecture specs into micro-architecture requirements, conduct performance/power model tasks, engage with SW teams for application modeling, and identify kernel-level hardware acceleration opportunities.

The Physical Design Engineer will perform synthesis, timing closure, and integration tasks, collaborating with the RTL team to optimize design flow.

The Performance Engineer - Inference will optimize model inference speed and throughput, debug low-level kernel performance, and develop tools to visualize performance data.

The Head of IT will build and manage the company's technology backbone, focusing on IT strategy, scaling, endpoint management, SaaS governance, and compliance while supporting rapid growth in a high-tech environment.

Lead post-silicon bring-up and optimization of wafer-scale engines: develop debug flows, HW-SW codesign optimizations, build large-scale test infrastructure, create self-checking metrics and instrumentation, and collaborate across silicon, performance, and software teams to improve production performance and release processes.

Build and maintain embedded and system-level software for the wafer-scale AI processor, including administrative services, Linux BSP support, hardware monitoring, diagnostics, and cross-team collaboration to improve reliability and observability.

Design and implement system-level debugging, validation, and observability platforms. Build automated anomaly detection, visualization and analysis tools, and frameworks for failure classification and regression detection. Extend compilers, runtimes, and instrumentation for advanced profiling. Improve bring-up and low-level debug workflows, partner cross-functionally across hardware, firmware, compiler and runtime teams, lead high-impact initiatives, and support incident response and long-term corrective actions.

As an ML Research Engineer, you will adapt and optimize language and vision models for efficient inference on Cerebras hardware, focusing on advanced techniques for low-latency, high-throughput performance.

Lead post-silicon bring-up and performance optimizations for Cerebras Wafer Scale Engines. Develop/debug production-ready flows, instrumentation, and self-checking metrics. Build infrastructure for large-scale silicon workload testing, collaborate with silicon architects, performance and software teams, and streamline CI/CD and release workflows.