Jobs at Cerebras Systems

Design and validate performance models, optimize and debug kernel microcode and compiler algorithms, analyze runtime and cluster performance, and build tools to visualize performance data for ML/LLM inference on the Cerebras Wafer Scale Engine.

The Applied Machine Learning Research Scientist will translate ML techniques into scalable systems, improve LLM performance, and optimize workflows while collaborating closely with researchers and engineers.

The Applied AI Scientist will develop large language models and deep learning solutions, customizing AI systems to meet client needs, and collaborate with stakeholders for project scoping and model architecture selection.

The Kernel Optimization Engineer will develop high-performance software solutions by optimizing deep learning operations and designing new machine learning kernels for the Cerebras hardware system.

The Design Verification Engineer will develop and implement verification strategies, collaborate with teams, and enhance verification methodologies for silicon designs.

Assist in deploying and monitoring Cerebras AI infrastructure, perform troubleshooting, collect telemetry, and learn through shadowing senior engineers.

Lead corporate FP&A operations including long-range planning, budgeting, forecasting, and executive reporting in a newly public AI chip company. Partner with leadership to drive decision-making and improve financial operations through technology and structured analysis.

Join the Kernel Reliability team to improve the reliability of compute clusters, assist in debugging, and enhance system tools alongside hardware teams.

The ML QA Lead ensures quality in Cerebras software across ML workloads, focusing on testing accuracy, performance, and usability. Responsibilities include driving software quality, automating workflows, debugging issues, and collaborating across teams.

The Senior WAN Network Engineer will design, implement, and manage global WAN services, ensuring high performance and reliability, while collaborating with telecom providers and optimizing network protocols.

The Deployment Engineer will build and operate AI inference clusters, ensure scalable deployments, optimize allocation, and maintain infrastructure. Responsibilities include software updates, telemetry development, and collaborative improvements with teams.

Join the Advanced Technology Group as a Compiler Engineer to design and develop the Tungsten language compiler for wafer-scale hardware, optimizing code generation for AI and scientific workloads.

The Senior Technical Program Manager is responsible for site and data center operations, leading cross-functional programs, ensuring operational readiness, and managing metrics and KPIs for AI infrastructure.

The Manufacturing Bring-up Engineer oversees system testing and validation, collaborating with cross-functional teams to automate workflows and enhance manufacturing efficiencies.

Support system-level bring-up processes in manufacturing, collaborate on automation and validate system performance, resolve technical issues and track metrics for continuous improvement.

Responsible for software integration and quality for Cerebras AI platform, focusing on automation, debugging, and cross-team collaboration. Develops QA strategies and testing methodologies to ensure product quality.

Design and develop high-performance distributed software for scalable AI training systems, focusing on data pipelines and system efficiency.

Develop and automate configuration for distributed clusters, create monitoring tools, manage cloud operations, and ensure system reliability for Cerebras AI supercomputers.

Lead a team to improve the reliability of advanced compute clusters and manage failure analysis and debugging processes.

Perform physical design and analysis for 3D integrated ASIC/SoC products, including full-chip and block-level physical verification, DRC/LVS resolution, IR/EM analysis, power/clock/cooling analysis, and 3D die stacking. Collaborate with RTL and architecture teams, optimize for power/performance/area, enhance flows via scripting, and work on packaging and floor-planning integration R&D.