Jobs at Black Semiconductor

Build full-stack features for the Black Net internal platform using Angular, Node.js, and MongoDB. Champion AI-augmented development by configuring coding assistants, integrating AI agents and automation, and enabling teammates through knowledge sharing. Collaborate with the Product Owner, contribute to architecture decisions, support ERP and procurement integrations, participate in code reviews, and improve engineering practices. The role may also involve LLM APIs, prompt engineering, Docker, and CI/CD pipelines.

Lead software architecture for a hybrid electronic/photonic compute engine: define programming model, compiler, runtime, and workload-placement strategies; develop AI workload performance models; co-design interfaces with hardware; prototype kernels, libraries, and runtime concepts to validate architectural decisions.

Lead hardware architecture for a hybrid electronic–photonic compute engine: define execution units, memory hierarchy, data fabric, interconnects, and hardware/software interfaces; perform quantitative modeling of performance/power/area trade-offs; collaborate across photonics, RTL, physical design, packaging, and software teams; own architecture specification through sign-off for silicon implementation.

Design and implement photonic integrated circuits: own schematic capture, mask layout, PDK-compliant tape-out readiness, DRC/LVS verification, workflow automation with Python, and collaborate with device, simulation, EIC, packaging, and foundry teams to deliver manufacturable PIC blocks and full-chip assemblies.

The Plating Process Engineer will develop and implement advanced plating processes, oversee fab startup activities, and establish specifications and protocols for plating tools in a semiconductor environment.

Lead tool planning and installation for plating capabilities in a semiconductor fab. Ensure safety compliance, drive equipment selection, and implement maintenance programs.

Lead EPIC SoC architecture from MRD to PRD, owning digital and high-speed I/O (SerDes, UCIe/PCIe/Ethernet). Integrate analog, photonics, memory, and packaging inputs, drive PPA trade-offs, vendor IP selection, modeling, and cross-functional alignment through product sign-off.

Lead end-to-end recruitment for specialized technical and operational roles (engineering, R&D, IC design, process development, manufacturing). Develop data-driven talent strategies, partner with hiring managers, improve recruitment processes using data and AI, collaborate with People team for onboarding, and track market trends to keep hiring competitive.

Partner with managers as a dedicated People Development lead to deliver performance and talent processes, enable career conversations, coach manager capability, run performance/talent review cycles, apply career frameworks, activate team learning, and support succession planning to scale a high-performance culture.

Manage end-to-end recruitment for technical and operational roles (engineering, R&D, IC design, process development, manufacturing). Partner with hiring managers, use data and AI to improve sourcing and processes, collaborate with People team, and monitor semiconductor talent market trends to attract high-quality candidates.

Drive the complete tape-out flow including DGS database integration, mask data preparation, and DfX co-integration for graphene photonic platforms.

Lead development and implementation of CMP processes for next-generation and 2D materials. Drive fab startup activities including tool installation, acceptance testing, recipe validation, and ramp-to-production. Define CMP tool/process specifications, establish Process of Record, implement SPC, and collaborate with suppliers, equipment, facility, and chemical/waste teams to integrate and qualify solutions.

Plan and execute product qualification campaigns for semiconductor photonic hardware. Develop test PCBs/fixtures with partners, set up and maintain lab equipment, run thermal/electrical/mechanical/environmental tests, collect and analyze data, coordinate with OSATs and external labs, and produce traceable qualification reports to support product release.

Own package reliability from mission-profile definition to qualification and release. Assess failure mechanisms, define and run reliability tests, lead failure analysis, work with OSATs and suppliers, and provide data-driven release recommendations.

Design, simulate, and validate high-speed analog transmitter and receiver circuits (transmit drivers, TIAs, limiting amps, CTLEs). Perform AC/transient/noise/jitter/PVT/Monte Carlo and post-layout simulations. Co-design electrical interfaces with photonics and packaging, support silicon bring-up, lab characterization, debugging, and correlate measurements with simulations to meet OCI Gen1/Gen2 performance targets.

Design, simulate, and validate analog/mixed-signal IP (LDOs, bandgaps, biasing, sensors, DACs/ADCs, calibration). Perform transistor-level simulations (DC/AC, transient, noise, stability, PVT, Monte Carlo), optimize power/area/noise/PSRR, support silicon bring-up and characterization, and collaborate with cross-functional teams from concept through silicon validation.

Lead analog/RF and high-speed SerDes architecture for CMOS SoCs enabling graphene photonic interconnects. Define PLLs, TIAs, drivers, equalizers, ADC/DACs, CDRs for 112G/224G+ PAM4. Produce PRSs and verification plans, close electrical-to-optical link budgets, own Analog IP roadmap, coordinate with photonics, package and SoC teams, engage customers, and incorporate interconnect standards like PCIe, UCIe, and CXL into architecture decisions.

Lead end-to-end ASIC and chiplet development programs combining electronics and photonics. Define milestones, manage schedules, risks, suppliers, and cross-functional execution through validation, qualification, and production release.

Own and scale People Operations and Global Mobility: payroll for NL and DE, contracts, HRIS administration, immigration and relocation programs, SOPs and process building, reporting and analytics, external partner coordination, and strategic business partnering to reduce manual workflows and support leadership in a fast-growing international environment.

Operate and maintain CD-SEM metrology tools to deliver accurate nanoscale measurements, support process control and yield improvement, perform maintenance and troubleshooting, collaborate with lithography/etch teams, generate metrology reports, train colleagues, and improve metrology methods while complying with EHS guidelines.