Jobs at Black Semiconductor

Design and validate broadband analog, RF, and high-speed mixed-signal IC blocks for graphene photonic communication and computing systems. Responsibilities include circuit simulation, PVT and Monte Carlo analysis, parasitic-aware layout collaboration, post-layout verification, silicon bring-up, laboratory characterization, debugging, and performance correlation. The role also involves cross-functional specification development and documentation with system, device, packaging, and product teams.

Leads the company-wide IT and technology strategy, enterprise infrastructure, engineering IT, cybersecurity, data and AI foundations, architecture, vendor governance, and technology operations. Builds the IT organization, hires leaders, establishes scalable operating processes, and partners with executive leadership, Engineering, and Fab-IT to support rapid growth.

Own and build the logistics and supply chain function as the company scales toward production. Lead logistics and warehouse teams, manage domestic and international transportation, optimize warehousing, inventory, material flow, and production support, and develop scalable processes. Drive SAP S/4HANA rollout, efficiency and delivery improvements, stakeholder collaboration, dangerous goods handling, import/export compliance, and regulatory adherence across operations.

Transforms graphene photonics characterization data into insights for device design, process development, and manufacturing. Owns analysis software and scalable data infrastructure, develops methods for evolving experiments, ensures data integrity and traceability, extracts device parameters, performs statistical and yield analyses, correlates measurements with process parameters, and integrates outputs with fab MES systems for real-time process feedback. Requires strong Python development, device physics knowledge, model fitting, visualization, and laboratory or fab instrument experience.

Own package reliability from mission-profile definition to qualification and release. Assess failure mechanisms, define and run reliability tests, lead failure analysis, work with OSATs and suppliers, and provide data-driven release recommendations.

Plan and execute product qualification campaigns for semiconductor photonic hardware. Develop test PCBs/fixtures with partners, set up and maintain lab equipment, run thermal/electrical/mechanical/environmental tests, collect and analyze data, coordinate with OSATs and external labs, and produce traceable qualification reports to support product release.

Design, simulate, and validate high-speed analog transmitter and receiver circuits (transmit drivers, TIAs, limiting amps, CTLEs). Perform AC/transient/noise/jitter/PVT/Monte Carlo and post-layout simulations. Co-design electrical interfaces with photonics and packaging, support silicon bring-up, lab characterization, debugging, and correlate measurements with simulations to meet OCI Gen1/Gen2 performance targets.

Lead end-to-end ASIC and chiplet development programs combining electronics and photonics. Define milestones, manage schedules, risks, suppliers, and cross-functional execution through validation, qualification, and production release.

Lead analog/RF and high-speed SerDes architecture for CMOS SoCs enabling graphene photonic interconnects. Define PLLs, TIAs, drivers, equalizers, ADC/DACs, CDRs for 112G/224G+ PAM4. Produce PRSs and verification plans, close electrical-to-optical link budgets, own Analog IP roadmap, coordinate with photonics, package and SoC teams, engage customers, and incorporate interconnect standards like PCIe, UCIe, and CXL into architecture decisions.

Own and scale People Operations and Global Mobility: payroll for NL and DE, contracts, HRIS administration, immigration and relocation programs, SOPs and process building, reporting and analytics, external partner coordination, and strategic business partnering to reduce manual workflows and support leadership in a fast-growing international environment.

Operate and maintain CD-SEM metrology tools to deliver accurate nanoscale measurements, support process control and yield improvement, perform maintenance and troubleshooting, collaborate with lithography/etch teams, generate metrology reports, train colleagues, and improve metrology methods while complying with EHS guidelines.

Lead customer integration of graphene photonic interconnects: guide bring-up, validation, debugging, develop reference designs and FPGA/ASIC demonstration platforms, support pre-sales and post-sales escalations, and feed field insights into product development.

Lead development and qualification of process flows and integration schemes for integrated graphene photonics. Plan, execute, and analyze integration studies, drive process optimization, yield and reliability improvements, and translate data into actionable recommendations. Collaborate cross-functionally and define process specifications for a 300 mm fab while managing projects and change-management for scale-up to volume manufacturing.

Lead software architecture for a hybrid electronic/photonic compute engine: define programming model, compiler, runtime, and workload-placement strategies; develop AI workload performance models; co-design interfaces with hardware; prototype kernels, libraries, and runtime concepts to validate architectural decisions.

Lead hardware architecture for a hybrid electronic–photonic compute engine: define execution units, memory hierarchy, data fabric, interconnects, and hardware/software interfaces; perform quantitative modeling of performance/power/area trade-offs; collaborate across photonics, RTL, physical design, packaging, and software teams; own architecture specification through sign-off for silicon implementation.

Design and implement photonic integrated circuits: own schematic capture, mask layout, PDK-compliant tape-out readiness, DRC/LVS verification, workflow automation with Python, and collaborate with device, simulation, EIC, packaging, and foundry teams to deliver manufacturable PIC blocks and full-chip assemblies.

The Plating Process Engineer will develop and implement advanced plating processes, oversee fab startup activities, and establish specifications and protocols for plating tools in a semiconductor environment.

Lead tool planning and installation for plating capabilities in a semiconductor fab. Ensure safety compliance, drive equipment selection, and implement maintenance programs.

Lead EPIC SoC architecture from MRD to PRD, owning digital and high-speed I/O (SerDes, UCIe/PCIe/Ethernet). Integrate analog, photonics, memory, and packaging inputs, drive PPA trade-offs, vendor IP selection, modeling, and cross-functional alignment through product sign-off.

Lead end-to-end recruitment for specialized technical and operational roles (engineering, R&D, IC design, process development, manufacturing). Develop data-driven talent strategies, partner with hiring managers, improve recruitment processes using data and AI, collaborate with People team for onboarding, and track market trends to keep hiring competitive.