Jobs at Axiado

Lead performance characterization and reliability validation for secure TCU/BMC systems. Design and execute benchmarking, stress, endurance, thermal, power, and error-injection tests; analyze bottlenecks and failures; perform root-cause investigations using hardware and firmware debugging tools; collaborate with engineering teams to resolve issues; maintain automated testing frameworks and reporting dashboards; and mentor junior engineers.

Provides technical leadership for Linux kernel and device-driver architecture, development, debugging, and optimization. Designs kernel modules, supports board bring-up, resolves complex hardware-software issues, profiles kernel performance, and collaborates with hardware and software teams on embedded-system integration. The role also contributes to the Linux kernel community and requires expertise in embedded Linux, BSPs, bootloaders, communication protocols, and low-level debugging.

Design, develop, and maintain BMC software for server products, including sensor monitoring, event logging, and web interfaces. Develop firmware for SPI, I2C, UART, and other peripheral protocols. Perform code reviews, unit testing, debugging, hardware troubleshooting, and BMC porting across multiple hardware platforms. Maintain technical documentation, user manuals, and release notes while supporting server power management and standards including IPMI, MCTP, and PLDM.

Develop and debug system-level verification environments, test plans, regression tests, stress and error-condition tests for complex ARM-based SoCs. Validate ROM and firmware, support emulation and simulation, debug RTL and device drivers, troubleshoot OS boots, and collaborate across hardware and software teams to identify root causes. The role also involves modeling SoC peripherals, validating interfaces, and supporting boot, security, recovery, and firmware-update mechanisms.

Run and debug system-level workloads on Synopsys ZeBu emulators, validate secure boot and platform security features, integrate and bring up transactors across high- and low-speed interfaces, manage regressions, and root-cause hardware, firmware, software, and test failures. Develop host-side automation and drivers, tune performance, and collaborate with RTL, design verification, and software teams to resolve system-level issues before silicon.

Lead system-level verification for complex ARM-based SoCs, developing simulation and emulation environments, test plans, stress and error-condition tests, and regression suites. Debug hardware, ROM, firmware, device drivers, and OS boot issues while collaborating across engineering teams. Validate connected interfaces and use waveform analysis, C programming, Python, Perl, shell scripting, and modeling tools throughout the ASIC project lifecycle.

Owns new product introduction from hardware design through volume manufacturing. Coordinates design engineers, contract manufacturers, suppliers, and operations; guides manufacturability and testing decisions; manages BOMs and part substitutions; drives manufacturing test development and execution; and maintains product documentation in PLM systems. The role is onsite in Taipei and supports products through production ramp.

Develops, debugs, and optimizes ATE and SLT test programs for silicon validation and production. The role supports NPI from silicon bring-up through mass production, defines test requirements, analyzes data to improve yield and reliability, maintains test patterns, supports digital and analog test interfaces, automates reporting, performs failure analysis, and drives improvements in test coverage, test time, and efficiency.

Develop and deploy machine-learning models across the stack, optimizing training and inference on GPUs and AI accelerators. Adapt models and runtimes to NPU and chip constraints, extend production silicon, and build firmware, embedded-system, testing, and verification solutions. Apply AI to cybersecurity and collaborate with hardware, RTL, firmware, and QA teams to deliver production AI features.

Develop and productionize ML models across the full stack, optimizing training and inference for GPUs, NPUs, and AI silicon. Build inference runtimes, MLOps pipelines, embedded system integrations, verification harnesses, and security-focused ML capabilities. Collaborate with hardware, RTL, firmware, and QA teams to deploy AI features under real-world latency, memory, power, and reliability constraints.

Optimize ML training and inference across GPUs and AI accelerators; design, train, evaluate, and productionize models; build inference engines and serving runtimes under latency, memory, power, and hardware constraints; and collaborate with hardware, RTL, firmware, and QA teams. The role requires expertise in at least one specialty such as NPU development, systems software, inference runtimes, verification harnesses, or cybersecurity-focused ML.

Lead cross-functional execution for ASIC SoC hardware and BMC software QA and design verification programs. Own schedules, dependencies, risks, milestones, metrics, defect lifecycles, system-level testing, automated regressions, emulation, FPGA development, and pre-silicon verification through deployment. Coordinate engineering teams across hardware, software, architecture, design, verification, validation, and system integration to maintain quality and tape-out readiness.

Develop and integrate secure AI server platform firmware for customer systems. Responsibilities include server bring-up, peripheral communication over low-level protocols, BMC software development, Linux kernel troubleshooting, secure boot and root-of-trust implementation, and platform integration across NVIDIA, Intel, and AMD architectures. The role also provides technical customer guidance, resolves complex integration issues, and supports custom hardware, embedded systems, microcontrollers, FPGAs, and ARM-based platforms.

Drive embedded computing hardware products from concept through production. Responsibilities include system design, hardware specifications, schematic capture in OrCAD, PCB layout coordination, signal integrity collaboration, lab bring-up, engineering validation, debugging, procurement, and cross-functional technical leadership. The role requires expertise in board design, high-speed interfaces, power conversion, server subsystems, lab equipment, and design validation, with 10+ years of hardware engineering experience.

Defines end-to-end system architecture spanning ASICs, SoCs, board-level platforms, firmware, and low-level software. Owns detailed architecture and microarchitecture specifications, hardware/software partitioning, security architectures, interfaces, and server platform integration. Engages enterprise customers, hyperscalers, standards organizations, and ecosystem partners while guiding hardware, signal integrity, power, thermal, firmware, and software teams. Requires deep server infrastructure, semiconductor, hardware security, board design, and production troubleshooting expertise.

Drive platform development and integration programs from planning through delivery. Manage schedules, milestones, dependencies, risks, issues, customer commitments, and cross-functional coordination across hardware, software, firmware, validation, and platform integration teams. Lead program reviews, customer communications, status reporting, platform bring-up, validation, qualification, and product readiness activities while improving program management processes.

Lead technical marketing for Axiado’s semiconductor, firmware, security, and software portfolio across APAC. Create technical content, presentations, solution briefs, competitive materials, and customer-specific collateral. Present to hyperscalers, CSPs, OEMs, and ODMs; support platform evaluations and design wins; contribute to launches and regional events; monitor competitors; and communicate APAC customer needs to headquarters. The role requires strong server hardware and data center infrastructure knowledge, technical customer engagement experience, English and Mandarin fluency, and regular APAC travel.

Lead firmware integration and validation for NVIDIA-based server systems. Diagnose NVSSVT and NVRAS failures, implement MCTP and PLDM communication, develop OpenBMC firmware, support NVIDIA RAS features, and integrate BMC management with NVIDIA GPUs, NVSwitches, Fabric Manager, and GPU software stacks.

Design architecture for System-on-Chips to enhance next-generation infrastructure, collaborating across hardware, software, and system disciplines.

Lead power-aware RTL/SoC verification: execute UPF-based simulations, integrate UPF with UVM testbenches and VIPs, create directed and constrained-random low-power tests, verify power gating/isolation/retention/reset across domains, develop assertions and coverage, support power-aware regression and sign-off, and collaborate with RTL and power architects.