Jobs at Axiado

Perform block- and subsystem-level ASIC physical implementation from netlist to GDS: floorplanning, placement, CTS, routing, timing closure, power and PPA optimization, physical verification, ECOs, signoff, and automation via Tcl/Python while collaborating with RTL/DFT/DV teams.

Lead and execute ASIC backend implementation from RTL handoff through tapeout. Own floorplanning, power/plaus, placement, CTS, routing, timing closure, ECOs, and signoff. Define physical verification/signoff methodology, debug complex signoff issues, drive automation and shift-left practices, and coordinate contractors, vendors, and cross-functional teams to meet tapeout quality.

Lead operations engineering functions for semiconductor manufacturing, oversee project collaborations, ensure product quality, and manage supply chain communications.

Lead integration of Secure AI engine into high-performance servers. Implement firmware for peripheral communication, port and maintain BMC software, troubleshoot platform issues, ensure secure boot and root-of-trust compliance, and collaborate with customers on platform bring-up and support for NVIDIA, Intel, and AMD systems.

Serve as the company's chief legal advisor, handling corporate governance, board and stockholder matters, contract negotiation, IP strategy, regulatory and compliance (including export controls and data protection), risk mitigation, transactions (financings, M&A), and oversight of international subsidiaries and local entity compliance.

Design architecture for System-on-Chips to enhance next-generation infrastructure, collaborating across hardware, software, and system disciplines.

Lead power-aware RTL/SoC verification: execute UPF-based simulations, integrate UPF with UVM testbenches and VIPs, create directed and constrained-random low-power tests, verify power gating/isolation/retention/reset across domains, develop assertions and coverage, support power-aware regression and sign-off, and collaborate with RTL and power architects.

The System Architect will design SoCs for transformative infrastructure products, develop specifications, and collaborate with various tech teams to establish standards.

Architect System-on-chips to transform next generation infrastructure products. Develop innovative specifications and collaborate with industry technologists on standards.

The System Architect will design System-on-Chips for next-generation infrastructure products, define hardware and software specifications, and collaborate with technologists to drive industry standards.

Lead the Quality Management System throughout the product life cycle to ensure high-quality semiconductor products. Responsibilities include designing and maintaining QMS, enforcing PLC processes, and managing product quality metrics while collaborating with functional teams and customers.

Lead finance to scale Axiado from late‑stage R&D to high‑volume semiconductor commercialization: run capital raises, FP&A and cash forecasting, standardize manufacturing costing and inventory accounting, manage vendor reconciliations and supply‑chain finance, upgrade ERP, optimize global tax and R&D credits, and ensure audit and compliance readiness.

Manage global HR operations including recruiting headcount and ATS optimization, payroll and EOR/vendor management, HRIS administration and integrations, international employment and visa/immigration compliance, benefits and LOA administration, performance cycle management, and employee communications for a mid-sized, globally distributed tech company.

The Senior Emulation Design Engineer will convert complex SOC designs into emulation environments, validate interoperability with AI servers, and optimize performance. Responsibilities include debugging, integrating IPs, and collaborating with multiple teams.

The Senior FPGA Design Engineer will engage in RTL design, FPGA simulation, system validation, and debug, collaborating with several teams in a fast-paced environment.

The Silicon Test Engineer at Axiado will develop, debug, and optimize ATE and SLT test programs while collaborating with cross-functional teams to ensure comprehensive test coverage for silicon validation and production.

The Staff ASIC Design Engineer will lead ASIC design projects, implement micro-architecture optimizations, and collaborate across teams to develop silicon products.

The ASIC Design Engineer will develop SoCs, optimize performance and power, collaborate with various teams, and support testing and validation processes.

The NPI Engineer will manage the transition of new products from design to manufacturing, collaborate with teams, analyze data, and improve processes.

Responsible for designing, developing, and maintaining BMC software solutions. Engage in firmware communication, code reviews, and ensure high-quality software through testing and debugging.