Teams at Altera (altera.com)

Design and implement DFT architecture and specifications for complex ICs (FPGA, processor, DSP, SERDES, multi-die). Insert test logic, run ATPG and pre-silicon validation, collaborate with IP/integration and test teams for silicon bring-up, debug, and production readiness. Improve DFT methodologies and automation to meet coverage, cost, yield, and manufacturability goals.

Develops and validates testability and manufacturability for integrated circuits from feasibility through production ramp. Designs test circuits, test flows, and hardware; performs ATE characterization and yield/bin analysis; debugs test/programming issues; collaborates with fab, assembly, quality, and design teams to enable post-silicon HVM ramp and optimize test, yield, and cost.

Provide customer-facing technical leadership for Ethernet FPGA IP: lead design bring-up and validation across 10G–800G, debug and optimize performance, validate protocol compliance (AN/LT, IEEE1588 PTP), produce reference designs and documentation, and collaborate with design, validation, product engineering, and sales to resolve issues and improve IP quality.