Teams at Altera (altera.com)

Architects FPGA IP for O-RAN, eCPRI, and CPRI applications in 5G networks. Leads customer and partner technical discussions while managing FPGA IP software, validation, and architecture teams. Oversees design, RTL development, simulation, hardware validation, troubleshooting, and debugging. Sets goals, coaches employees, manages performance, and ensures teams deliver results. Requires expertise in FPGA development, wireless standards, timing closure, clock-domain crossing, reset architecture, and standard interfaces.

Designs and verifies synthesizable RTL and DSP algorithms for mixed-signal IP, including SerDes, ADC/DAC, calibration, equalization, and clock/data recovery systems. Responsibilities include microarchitecture, synthesis, timing closure, low-power design, AMS co-simulation, silicon bring-up, laboratory debugging, documentation, code reviews, and mentoring junior engineers. Collaborates closely with analog teams on digital-analog interfaces and adaptive control flows.

Lead end-to-end FPGA development kit execution across board architecture, RTL, firmware, validation, manufacturing, and supply chain. Coordinate global engineering teams, design partners, ODMs, contract manufacturers, and suppliers. Drive BOM planning, cost optimization, component availability, obsolescence management, technical risk resolution, manufacturing execution, and platform robustness improvements.