You will architect and develop IP blocks for CXL/PCIE ASICs/FPGA, lead projects, streamline processes, and manage team development.

Lead global tax strategy, compliance, and reporting. Manage tax audits, optimize tax positions, and improve processes while overseeing international tax regulations.

Work with engineering teams to develop ATE solutions for high-speed SOCs, support product testing, and reduce production costs through effective test strategies.

The Senior Design Verification Engineer manages end-to-end verification of IP subsystems, builds testbenches, analyzes bugs, and collaborates with multiple teams.

The Senior Staff Engineer II will lead SERDES sub-block designs, mentor junior designers, and ensure circuit designs meet specifications with a focus on high-speed analog circuits.

Lead SERDES sub-block design, mentor junior designers, and ensure quality circuit design and validation at high speeds for advanced analog products.

Responsible for verification of IP, Block, or Subsystem at SoC Level; developing documentation and verification environments; analyses, and debugging tasks; reports to Lead Engineer.

Lead technical design in analog circuits focusing on SerDes, mentor junior engineers, and ensure compliance with system specifications through documentation and simulations.

The Staff DFT Engineer will architect DFT methodologies, automate RTL for DFT features, and develop verification solutions for SoC designs.

The role involves hands-on physical design and verification of ASIC projects, managing ASIC development flow, mentoring junior team members, and ensuring integration of IP and pad-rings in designs. Key tasks include floor-planning, place and route, timing closure, and debugging.

The Senior HR Business Partner will partner with leadership to implement HR strategies, enhance employee engagement, manage organizational change, and ensure compliance with policies.

The Staff Engineer will lead SOC EMIR analysis, collaborate with teams for design changes, mentor juniors, and influence analysis workflows.

The Senior Product Line Manager will drive product strategy and development for high-speed semiconductor products, ensuring alignment with customer needs and market trends.

Lead the verification for SoC System Manager, oversee verification activities, collaborate with design teams, and develop scalable testbench components.

Define debug strategies for multi-core ARM SoC designs, create architecture documentation, integrate RTL, perform synthesis, and collaborate on debug processes.

Design Engineer will manage the IO Memory Management Unit components for a multi-core Arm CPU based SOC, focusing on architecture, design, and STC integration while collaborating with teams on verification and debugging.

The Design Engineer will lead the Interrupt Subsystem components for multi-core ARM-based SoCs, conduct RTL coding and integration, and support design and validation activities within a collaborative engineering environment.

The Senior Engineer - STA will lead the timing convergence for SoCs, manage timing constraints, and oversee timing analysis and closure efforts.

Lead the timing convergence of SoCs, manage STA setup and full chip timing analysis, develop automation scripts, and collaborate with various teams for design and verification.

The Staff DFT Engineer will develop and manage DFT methodologies, automate verification processes, oversee team tasks, and mentor engineers for complex SoC designs.