The Senior Engineer will conduct EM and IR analysis for Power Delivery Networks and Standard Cell designs, mitigate potential IR drop issues, and collaborate with stakeholders to enhance power distribution. Responsibilities include tool development for automating the IR drop analysis process and providing recommendations based on analysis results.

Design custom analog layouts for high-speed SerDes IP, collaborate with teams, optimize layouts, and perform physical verification in semiconductor technology.

The Staff Engineer will design and develop microarchitecture and RTL for SoC subsystems, collaborate across teams, and ensure design quality and successful tapeout.

Lead design and architecture for SoC subsystems focusing on boot, security, and power management while collaborating with verification teams and defining performance metrics.

Design custom analog layouts for high-speed SerDes architectures, collaborate with analog design teams, and perform physical verification in advanced semiconductor nodes.

The Principal Program Manager will oversee project schedules, execution tracking, risk mitigation, and process frameworks in semiconductor projects.

The Senior Application Engineer is responsible for customer support with Ethernet and PCIe serdes IPs, engaging with R&D teams and resolving issues.

The Analyst will manage payroll, accounts payable, financial reporting, and enhance finance processes through automation and collaboration.

The role involves delivering compliant IP blocks for ASIC/FPGA, leading projects, developing verification environments, and mentoring junior engineers.

The role involves designing, simulating, and testing optical systems for data transmission, focusing on PAM4 modulation with hands-on laboratory measurements and DSP algorithm development.

Provide first-line customer support for Ethernet/PCIe controller IPs, work with R&D, and develop APIs while assisting in post-sales silicon bring-up and testing.

As a Senior Staff Physical Design Engineer, you'll implement and verify complex digital designs, focusing on physical implementation including timing closure and physical verification for advanced nodes.

Manage ASIC physical design tasks including floor-planning, timing closure, and verification for advanced process nodes. Mentor junior team members.

Lead firmware development for UCIe chiplets, collaborating with teams from design to validation, ensuring high-quality firmware through best practices, mentoring engineers, and managing timelines.

As a Product Applications Engineer, you'll drive technical support for customers, author technical documents, and ensure successful product integration while collaborating with multiple teams.

The role involves driving backend processes, optimizing design for power and area, and ensuring timing closure and physical verification for IC design.

Manage NetSuite projects, providing support and oversight for implementations, testing, reporting, and user training while driving process improvements.

Analyze EM and IR for power delivery networks. Collaborate with teams for design recommendations and tool automation for IR drop analysis.

The role involves hands-on physical design and verification tasks, managing ASIC development flows, mentoring junior team members, and ensuring correct IP integration.

Lead a team in SoC architecture and design, optimize design processes, interact with customers, and ensure product quality and performance for Chiplet systems.