Search the 63 jobs at Alphawave IP, Inc.

As a Test Engineer Manager, you will manage a team of test engineers, oversee ATE test module development, collaborate across various teams for product launch, and ensure high-quality testing standards. Responsibilities include mentoring team members, leading design and implementation of testing processes, and traveling to vendor sites as needed.

As a SoC/System Architect, you will drive the architecture of ARM Neoverse-based chiplets, define system-level use cases, document performance metrics, and collaborate with design teams while engaging with customers for pre-sales activities. You will specify IP and document architecture and integration.

The Principal Digital Verification / Lead Engineer will lead the verification team, overseeing the verification process for ARM Neoverse-based Multi-CPU SoCs. Responsibilities include developing verification plans, creating reusable testbenches, mentoring junior members, and collaborating with design teams to ensure accurate verification of subsystems and architectures.

In this role, you will manage all aspects of the US immigration process, including client communication, document gathering, and application submission for various visa types. The position involves preparing petitions, providing consular support, and improving processes while meeting client deadlines.

The Staff Engineer I for STA and Synthesis will lead static timing analysis and synthesis for complex ASIC designs, collaborate with various teams on timing optimization, and develop timing constraints using scripting languages. The role emphasizes leadership and communication skills to drive design closure and efficiency, while staying updated with emerging technologies in ASIC design.

As a Senior Staff Engineer I - RTL Design, you will lead the design and architecture of SoCs and micro-architecture, manage a design team, engage in pre-sales support, and ensure timely project delivery. Your expertise will support customers in implementing data communication solutions across various applications while fostering improvements in design methodologies.

As a Senior Engineer in Physical Design, you will drive the backend processes of IC design, focusing on floor-planning, power planning, low-power design, place & route, and static timing verification. You'll perform physical verification and EM/IR signoff to optimize power integrity and timing closure. The role requires collaboration, analytical skills, and a commitment to high-quality results.

The Design Verification Engineer will lead the verification of new customer features, review design specifications, build testbenches, and analyze test failures. The role involves collaborating with multiple teams, integrating third-party VIPs for compliance testing, and contributing to the improvement of verification methodologies.

Responsible for verification of IP, Block, or Subsystem at SoC Level, generating documentation, debugging verification tasks, and developing the verification environment and components. Requires a strong understanding of functional verification and experience with various interfaces and methodologies.

The Senior Engineer II - ASIC Design will focus on accelerating critical data communication technologies for sectors such as AI, 5G, and autonomous vehicles, contributing to innovative solutions in a diverse workplace.

In this role, you will lead the verification of IP and sub-systems, develop scoreboard mechanisms and monitoring for issue detection, create verification environment components, code tests and assertions, and ensure functional coverage while debugging failures and managing regression testing.

The Staff Program Manager will oversee project schedules, track milestones, and align strategies with the management team. Responsibilities include working with team leads to refine work breakdown structures, managing internal signoffs, and driving process frameworks for efficient execution and deliverables quality.

As an ASIC/FPGA Designer, you will develop and validate digital designs, writing RTL code, resolving lint errors, and achieving timing closure. Your role includes delivering compliant IP blocks for FPGAs/ASICs, streamlining processes, collaborating with teams, and mentoring junior engineers.

The Senior Analog Design Engineer will develop and optimize analog block performance while handling circuit implementation, layout, and design strategies. Responsibilities include characterizing circuits, overseeing physical layouts, and collaborating with application teams.

The Staff Design Verification Engineer at Alphawave Semi will architect, design, and verify DSPs using high-speed mixed-signal PHYs. Responsibilities include developing scalable testbench components with UVM, overseeing the verification process, collaborating with design teams, and mentoring junior members.

As a Principal Engineer - RTL Design at Alphawave Semi, you'll lead a team in micro-architecture development, oversee pre-sales architectural proposals, manage design team deliverables, and collaborate with customers and IP vendors to meet project goals while improving methodology for high reuse.

As a Mixed-Signal Engineer in the CTO Office, you'll develop high-performance analog and mixed-signal circuits for next-generation products, particularly focusing on 100+Gbps serial transceivers using advanced CMOS technologies. You'll engage with the CTO and engineering teams, define specifications, drive design and layout, and ensure performance targets are met through collaboration and hands-on experimentation.

As a Connectivity Systems Engineer, you'll develop next-generation optical and electrical connectivity technologies. Responsibilities include system-level simulations of high-speed electrical and optical links, enhancing simulation platforms, deriving specifications, and collaborating on prototypes. The role supports AI and networking advances, contributing to internal and external presentations.

The Senior/Staff/Principal Product Applications Engineer will provide technical support for customers using Alphawave's DSP chips, ensuring integration into customer designs and working closely with internal teams. Responsibilities include authoring technical documentation and validating product performance, with potential travel required for customer engagement.

The Staff DFT Engineer will develop and support DFT methodologies, automate verification test benches, and build scan insertion flows for SoCs. The role involves architecting integrated RTL-centric DFT environments and ensuring quality control for DFT designs across various complex systems.