Search the 60 jobs at Alphawave IP, Inc.

The APAC Country Manager is responsible for overseeing all operations in the APAC region, fostering relationships with stakeholders, managing financial performance, ensuring compliance, leading local strategic initiatives, and reporting to corporate management while building and leading a team.

In this role, you will lead customer engagements and manage ASIC product programs from concept through mass production. Responsibilities include planning and budgeting, tracking program performance, customer feedback management, and regular communication with internal teams and executives. You will ensure that products meet customer expectations while overseeing technical and managerial aspects.

The Staff Design Verification Engineer at Alphawave Semi will architect, design, and verify DSPs using high-speed mixed-signal PHYs. Responsibilities include developing scalable testbench components with UVM, overseeing the verification process, collaborating with design teams, and mentoring junior members.

The Staff Engineer II - Analog Layout will lead layout design activities, produce high-quality IPs and work closely with the design team. Responsibilities include area estimation, floor planning, and verification processes, along with mentoring junior engineers and developing scripts.

In this role, you will lead the verification of IP and sub-systems, develop scoreboard mechanisms and monitoring for issue detection, create verification environment components, code tests and assertions, and ensure functional coverage while debugging failures and managing regression testing.

The Physical Design Engineer will work on advanced place and route flow using CAD tools, collaborating with design and verification teams, integrating complex analog IPs, and performing physical verification tasks. Responsibilities include block and chip level floor-planning and developing layout software automation capabilities.

As a Staff Engineer I for RTL Design, you will lead architecture proposals, manage design teams, and ensure delivery on various key projects aligning with ARM architecture and IP integration, while overseeing progress with cross-functional teams.

Responsible for the verification of IP, Block, or Subsystem at SoC Level, including generating documentation, debugging, and developing verification environments. Requires expertise in digital verification methodologies and protocols.

The Senior Staff Engineer I will perform physical design and verification tasks on ASIC projects, managing development flows in advanced process nodes. Responsibilities include floor-planning, timing closure, and coordination of verification activities while mentoring junior team members.

The Staff Engineer I - Physical Design will handle physical design and verification tasks for ASIC development, including floor-planning, timing closure, and IR/EM analysis. The role involves mentoring junior team members and ensuring the integration of different design components. Reporting to the ASIC Design Director, the engineer will work in a hybrid environment managing project-specific workflows.

Responsible for verification of IP, Block, or Subsystem at SoC Level, generating documentation, debugging verification tasks, and developing the verification environment and components. Requires a strong understanding of functional verification and experience with various interfaces and methodologies.

The Principal Engineer - SOC Verification is responsible for verifying IP, Block, or Subsystem at SoC Level, developing and owning the verification environment, and generating necessary documentation. The role requires an understanding of the verification flow, experience with digital verification aspects, and proficiency in various protocols and scripting languages.

Perform physical design and verification tasks in advanced process nodes for ASIC development. Mentor junior team members and ensure IP integration. Reporting to ASIC Design Director.

As an IP Applications Engineer at Alphawave Semi, you will provide first-line technical support for Ethernet and PCIe controller IPs, HBM controllers, and more. You will engage with R&D teams to assist customers in integration and silicon bring-up, develop APIs and ATE vectors, and resolve integration issues.

The Senior Staff Engineer I - DFT will lead the development of DFT methodologies and automated verification systems. Responsibilities include architecting DFT flows, mentoring engineers, and ensuring integration of custom DFT logic for SoC designs, while collaborating with various teams on innovative solutions.

The Principal Engineer in Physical Design will manage ASIC development processes, perform physical design and verification tasks, mentor junior team members, and ensure high-speed design implementation. The role involves hands-on tasks like floor-planning, timing closure, and running verification scripts.

The Talent Acquisition Manager will lead the recruitment team, manage strategic initiatives, and ensure compliance of ATS information. Responsibilities include coaching TA team members, analyzing recruitment metrics, improving candidate experience, and enhancing collaboration with hiring managers to create competitive offers.

The Staff Recruitment Specialist will actively source candidates for VLSI and semiconductor positions, manage the recruitment process, collaborate with hiring managers, enhance the company's brand, and ensure a diverse hiring process while providing positive candidate experiences.

As a Principal Applications Engineer at Alphawave Semi, you will provide front-line technical support for Ethernet and PCIe SerDes IPs, assist customers with post-sales integration and silicon bring-up, and collaborate with R&D teams. You'll develop APIs, maintain ATE vectors, and resolve customer issues, leveraging your extensive technical expertise.

The Senior Engineer II - VLSI will deliver standards-compliant IP blocks for OTN, Ethernet, CXL, and PCIe FPGAs or ASICs, lead projects, streamline development, micro-architect designs, and mentor junior engineers. Key skills include knowledge of telecommunications protocols and experience with verification tools and various programming languages.