Develop test environments for block and cluster levels, collaborating with design and algorithm teams using SystemVerilog UVM and Formal verification.

Seeking a Senior ATE Test Engineer to evaluate design specifications, develop analog/digital test modules, and collaborate with various teams to ensure successful product launches.

Lead and manage a verification team, developing verification plans for complex hardware designs, ensuring quality and functionality of products.

The DFT Engineer will manage the end-to-end custom silicon design cycle, lead DFT architecture planning, and collaborate with cross-functional teams to ensure effective DFT implementation and verification.

As a DFT engineer, you will lead the implementation of DFT architectures and collaborate with cross-functional teams to deliver custom silicon solutions.

As a DFT engineer, responsible for end-to-end custom silicon design including DFT architecture, scan and MBIST implementation, and collaboration with cross-functional teams.

As a DFT Engineer, you will develop and implement DFT architectures, verify solutions, and work with RTL and Test teams to resolve issues.

Lead static timing analysis and synthesis for complex ASIC designs, collaborate with teams to optimize performance, develop timing constraint sets, and manage project timelines.

The DFT Engineer will develop and implement DFT architectures, execute verification plans, and collaborate with RTL and Test teams to enhance custom silicon lifecycle processes.

As a DFT Engineer, you'll implement and verify DFT solutions, develop architectures, and collaborate on test techniques within custom silicon. Responsibilities include documentation and resolving DFT issues.

The Senior Staff Engineer II - DFT will lead the implementation of DFT architectures, work on large designs, develop DFT verification plans, and collaborate with cross-functional teams.

The DFT Engineer develops and implements DFT architectures, collaborates with teams, and executes verification plans throughout the custom silicon lifecycle.

Develop and support DFT methodologies and flows for integrated RTL DFT environments, and automate verification and timing checks across projects.

The Senior Product Applications Engineer will provide technical support to customers, collaborate with internal teams, and ensure product integration and performance validation in optical transceiver designs.

As a Senior DFT Engineer, you'll develop and maintain DFT methodologies, create automated verification, and lead DFT engineers.

The IP Applications Engineer provides post-sales support for Ethernet/PCIe and HBM IPs, assists customers with integration, and collaborates with R&D.

Develop Interface and Analog IPs for ASIC projects, focusing on Analog and mixed signal designs. Collaborate with customers and deliver complex IP functionalities.

Develop and maintain DFT methodologies and flows, automate verification test benches, and ensure quality control in complex SoC designs.

Develop test environments for block and cluster level, collaborate with Design and Algorithm teams, and work on advanced high-speed products using SystemVerilog UVM and Formal verification.

Responsible for PCIe IP design and integration, including microarchitecture, RTL coding, and collaboration with verification teams for effective design delivery.