Top Engineering Jobs

Senior PCIe Verification Engineer responsible for creating and executing verification plans and testbenches for PCIe IP/SoC, debugging designs, collaborating with RTL designers and validation teams, and ensuring protocol compliance and quality.

Design and integrate PCIe, CXL, UCIe and other I/O subsystems into SoCs. Write micro-architecture specs, develop RTL in Verilog, run static checks, debug builds, collaborate with verification, performance, and backend teams, and mentor others to deliver complex SoC projects.

Verify PCIe/CXL high-speed IOs at subsystem level: create verification strategies and test plans, develop SystemVerilog/Verilog/UVM testbenches, run simulation and emulation, analyze performance and interoperability, debug issues, improve methodologies, and mentor junior engineers while collaborating with architects and project management.

Design and integrate PCIe, CXL and other subsystems for SoCs: write micro-architecture specs, develop RTL in Verilog, debug, run static checks, collaborate with verification, performance analysis and backend teams, and mentor team members.

Drive SoC and server platform performance by characterizing real-world AI/HPC workloads on production silicon, designing microbenchmarks, diagnosing bottlenecks, and translating findings into architectural and system-level optimizations while collaborating with hardware and software teams.

Lead workload and silicon-level performance analysis for next-generation server platforms (AI at scale and HPC). Define metrics and benchmarks, build microbenchmarks, identify bottlenecks, recommend architectural optimizations, and collaborate with hardware and software teams to validate improvements end-to-end.

The Principal High-Speed I/O Architect designs interconnect architectures for SoCs, collaborating on performance and efficiency in various markets.