Top Engineering Jobs

Architect high-speed PCIe, CXL, and UA Link interconnect subsystems for scalable Arm-based SoCs. Define technology roadmaps, develop implementation-ready specifications, integrate coherent and non-coherent architectures, and optimize bandwidth, latency, power, and performance. Collaborate with customers and multidisciplinary hardware, software, firmware, physical design, and platform teams while guiding workload analysis, performance modeling, and end-to-end system solutions.

Verifies security IP and embedded processor subsystems for SoC designs. Responsibilities include creating test plans, UVM/SystemVerilog/Verilog/C testbenches and tests, developing verification models, debugging failures, achieving functional coverage, and supporting power and performance optimization. The role also contributes to verification methodologies, hardware/firmware co-verification, formal verification, and project initiatives. Security domains include cryptography, secure boot, key management, and hardware roots of trust.

Enable advanced semiconductor process nodes by developing and optimizing EDA design flows, methodologies, scripts, automation, and CAD solutions for CPU designs. Analyze floorplanning, power delivery, timing, power, physical design, and PPA. Drive technology enablement from early development through production, integrate external EDA tools, collaborate with vendors and foundries, and lead product implementation with cross-functional teams.

Staff PCIe Verification Engineer role at Arm focused on PCIe technology verification. The provided description contains no specific responsibilities or qualification requirements beyond the staff-level title and compensation information. The position supports Arm’s collaborative, hybrid working environment and emphasis on innovation, inclusion, and responsible use of AI during the application process.

Owns secure semiconductor manufacturing test and provisioning on Advantest 93K ATE. Responsibilities include test architecture, SmarTest program development, first-silicon bring-up, characterization, HSIO and structural test integration, hardware coordination, silicon and ATE debug, production release, OSAT deployment, yield improvement, and high-volume manufacturing readiness.

Owns ATE test enablement, first-silicon bring-up, characterization, debugging, and production release for complex SoCs on Advantest 93K. Develops SmarTest programs, test methods, patterns, flows, binning strategies, and production content across wafer sort, final test, SLT, OSAT, and HVM. Leads ATE hardware readiness, HSIO validation, correlation, yield debugging, and cross-functional execution with design, DFT, firmware, vendors, contractors, and manufacturing partners.

Leads SoC power analysis, modeling, optimization, and pre- and post-silicon power convergence. Manages and mentors power engineers while coordinating with architecture, design, verification, and product teams. Drives power targets, develops workflows, creates workload scenarios, improves silicon correlation, and supports power sign-off. Requires expertise in RTL and netlist power analysis, EDA tools, ASIC design dependencies, simulation and emulation environments, and multi-project technical leadership. Python automation and power-budget decomposition are preferred.

Leads SoC power analysis, modeling, optimization, and pre- and post-silicon power convergence. Manages and mentors power engineers while collaborating with architecture, design, verification, and product teams. Defines power methodologies, workflows, budgets, and sign-off processes; develops workload scenarios; improves accuracy and silicon correlation; and drives performance-per-watt targets throughout the SoC lifecycle.

Staff Design Engineer role at Arm with a stated annual salary range of $198,100 to $268,000. The provided description contains company values, hybrid-work information, application guidance, accommodations, and equal-opportunity statements, but does not specify technical responsibilities, required qualifications, technologies, travel, or clearance requirements.

Build and operate scalable platform services and APIs that improve engineering workflows. Develop Kubernetes operators, automate self-service capabilities, provision cloud infrastructure with Terraform, and manage reliable workloads using AWS, Docker, Kubernetes, Helm, and ArgoCD. Lead technical initiatives, apply secure software engineering practices, support production systems, and participate in an on-call rotation while collaborating across engineering teams.