Top Engineering Jobs

Architects, implements, and validates design-for-test techniques for Arm SoCs and subsystems. Responsibilities include DFT insertion, RTL and gate-level simulation, ATPG pattern generation, coverage debugging, DFT timing analysis, scan insertion, timing closure, ATE test validation, silicon debug, and characterization. The role collaborates with RTL, verification, physical implementation, test, and product engineering teams throughout development and tape-out.

The IP Verification Engineer is responsible for developing testbenches and test suites, writing test plans, and collaborating with design teams to ensure quality verification of complex subsystems and SoCs.

The Senior/Staff Design Verification Engineer will be responsible for design verification in coherent interconnects. Specific responsibilities are not detailed, but expertise in this area is expected.

Develop and improve front-end ASIC/SoC build methodologies, CAD flows, and automation from RTL development through implementation handoff. Build production-quality infrastructure for RTL quality, verification, IP management, regression, and release readiness. Collaborate with engineering teams and EDA vendors to resolve bottlenecks, evaluate AI and automation technologies, and drive methodology adoption across projects.

Architect and design high-volume SoC platforms using Arm IP across mobile, automotive, datacenter, networking and IoT. Lead cross-functional teams to define platform architecture, optimize performance and power, coordinate IP delivery, drive partner engagements, and influence roadmap and feature development. Guide specification maturity and ensure on-time delivery while driving innovation and continuous improvement.

The SoC RAS Architect drives reliability and serviceability strategies for SoCs, ensuring compliance with data center standards through collaboration with design and engineering teams.

Lead full-chip and block-level timing closure for complex SoCs across project lifecycle. Define and manage timing constraints, collaborate with cross-functional teams and EDA vendors, perform ECOs, address timing for multiple power domains and advanced nodes (5nm/3nm), and automate flows using scripting.

Lead quality, functional safety, and automotive cybersecurity compliance for semiconductor and SoC programs. Develop scalable ISO 26262 and ISO/SAE 21434 approaches, align engineering practices with standards, prepare certification evidence, support external assessments, conduct audits, and drive process improvements, training, corrective actions, and safety readiness across automotive, robotics, AI, and industrial products.

Develop and execute verification strategies for sophisticated Arm SoCs and compute subsystems. Responsibilities include reviewing architecture, creating test plans, developing SystemVerilog and Verilog testbenches, debugging failures, verifying PCIe/CXL, DDRx/LPDDRx, and HBM subsystems, improving methodologies, and supporting project planning and junior engineers.

Provide technical mentorship and support to partners integrating Arm CPUs and System IP into SoCs. Perform RTL simulation-based debugging, SoC build reviews, deliver training, influence IP development, test IP, and create knowledge-base content and tooling to improve partner outcomes.