Top Engineering Jobs

Lead analog design efforts for high-speed PHY sub-blocks at advanced process nodes (12nm and below). Own specifications and implementation, collaborate with a skilled analog team, and leverage AI-assisted design workflows where applicable.

The Staff Engineer will lead HBM validation efforts, develop test programs, conduct advanced analysis, mentor junior engineers, and collaborate across teams. Responsibilities include validation execution, platform leadership, debugging, and continuous improvement.

The HVM EE PVD Engineer will work on equipment start-up and productivity improvement in PVD processes, aiming to enhance product quality and reliability, while also improving yield and reducing costs through problem-solving and precision methodologies.

Lead development and optimization of wafer and die processing equipment, create multi-year hardware roadmaps, collaborate with process teams and OEM vendors, perform root-cause and failure-mode analysis, drive FOAK equipment maturity, support production transfers, and apply AI-driven solutions to improve capability, cost, and availability.

Drive improvements in labor productivity and operational efficiency through program management, data-driven insights, and automation solutions in semiconductor operations.

As a Senior Member of Technical Staff, you'll lead the development and integration of 3D NAND processes, focusing on innovation, performance optimization, and cross-functional team coordination.

The Package Health Test Engineer develops and executes package health monitoring, including DFT, data analysis, and reliability testing for semiconductor packaging solutions.

Develops and implements semiconductor metrology techniques, including lithography overlay, CD-SEM, ellipsometry, scatterometry, XRF, and surface profiling. Supports process and equipment evaluations, supplier tool continuous improvement, new product introduction, quality metrics, and fab operations. The role focuses on improving yield, quality, cost, cycle time, measurement capabilities, and process characterization while standardizing best practices and applying AI-enabled tools, automation, and data-driven insights.

Design and analyze digital and analog DRAM circuits for advanced HBM products, performing simulation, optimization, floorplanning, and trade-off analysis for timing, power, and area. Evaluate block- and full-chip functionality, perform architectural pathfinding, and collaborate with design and verification teams to ensure correctness and performance of next-generation HBM designs.

Own block-level analog, mixed-signal, and custom digital layout for advanced CMOS designs. Perform DRC, LVS, antenna, yield, and quality verification; support chip integration, ECOs, and layout closure. Develop AI-assisted SKILL, Python, and Tcl automation to improve efficiency and consistency. Collaborate with design, verification, CAD, and senior engineers while mentoring junior layout developers.