Top Engineering Jobs

Define and implement NAND Flash reliability test flows, perform large-scale statistical analysis and electrical failure analysis, develop countermeasures and qualification controls, collaborate with cross-functional teams, integrate AI-assisted tools, support customer reliability inquiries, and drive strategic reliability initiatives to ensure robust NAND product performance and prevent field escapes.

Manage and improve wafer fabrication processes, troubleshoot issues, conduct root cause analysis, and assess product specifications.

The Sr. Design Verification Engineer will validate complex SoC designs, develop verification environments using UVM and SystemVerilog, enhance Python-based testbenches, and collaborate closely with design teams to ensure high-quality silicon delivery.

The role involves planning facility changes, coordinating with engineering firms, managing construction contracts, and ensuring compliance with safety codes and regulations.

Lead R&D and operations in advanced metrology processes, develop methods for accuracy and precision, and mentor engineers in a semiconductor manufacturing context.

The role involves establishing and improving process conditions and technologies, enhancing process capabilities, and conducting evaluations and planning for new equipment and materials in semiconductor manufacturing.

The Principal Engineer for HBM Design for Test (DFT) will define and implement DFT solutions, ensuring alignment with design and verification while driving standardization across HBM products.

Lead dry etch process development for 3D NAND: deploy new process technologies, optimize etch tool performance and recipes, run DOE and data analysis, troubleshoot yield issues, collaborate with fabs and cross-functional teams, and apply AI to streamline workflows and decision-making.

The role involves process and equipment responsibilities in dry etching for advanced DRAM production, focusing on improving yield, productivity, and supporting new equipment introduction.

Design and implement DFT (scan, MBIST, LBIST, boundary scan) for SOCs and hard macros. Generate and validate ATPG patterns, perform RTL and gate-level verification, support silicon bring-up, and collaborate with STA, synthesis, verification, test, and product teams to improve DFT methodology and test stability.