Top Engineering Jobs

Supports a semiconductor test engineering project focused on improving burn-in equipment availability and Parts per Jam. Responsibilities include structuring alarm data, analyzing downtime patterns, developing predictive analytics, creating automated notifications and visualizations, validating trigger logic, and evaluating socket-masking and Agentic AI solutions. The intern will use Python, SQL, Power BI, and Power Automate while learning semiconductor test processes and equipment monitoring.

Analyze inline, parametric, probe, and experimental data to identify wafer-yield limiters and resolve process or tool issues. The engineer applies semiconductor device physics, electronics, manufacturing-process knowledge, and statistical analysis to improve yield, quality, and technology ramp. Responsibilities include communicating yield findings, creating Pareto analyses, collaborating across Fab and Yield Enhancement groups, supporting cross-functional problem-solving teams, transferring new technologies into production, and responsibly integrating AI-assisted tools.

Develop and support automation, AI, data integration, reporting, and analytics solutions for Facilities. Evaluate AI use cases, integrate capabilities with enterprise systems such as SAP and ECBP, optimize workflows, and improve operational decision-making. Lead projects from requirements through implementation, adoption, and change management while ensuring reliability, scalability, compliance, and business value. Collaborate across engineering, construction, operations, sustainability, EHS, and project teams, and coach others on automation and AI tools.

Intern will optimize semiconductor manufacturing layout planning for an MSH probe ramp. Responsibilities include conducting site assessments, evaluating installation readiness, mapping workflows, identifying bottlenecks, and developing AI-enabled automation using tools such as Power Automate, Python, SQL, and Microsoft Copilot. The intern will collaborate with engineering and production stakeholders, apply responsible AI practices, measure project benefits, and document solutions and user guidance.

Supports legacy DRAM products through electrical and physical failure analysis, yield improvement, reliability enhancement, and root-cause investigations. Uses statistical analysis, data visualization, and AI-supported workflows to identify fabrication, assembly, and testing issues. Collaborates with Product, Process, Quality, and Test Engineering teams to resolve defects and improve component performance. Communicates technical findings through reports and presentations.

Lead or support PCRB reviews for semiconductor process, equipment, material, and system changes. Conduct risk assessments using PPA, FMEA, and scenario analysis; identify mitigation actions; and investigate post-conversion quality issues. Collaborate with cross-functional and cross-site teams, maintain conversion metrics and records, support audits, and improve quality governance systems and dashboards. Provide independent, data-driven quality judgment for conversions, transfers, qualifications, and production process improvements.

Lead NAND cell integration efforts by driving process and device technology development, designing experiments, analyzing inline/probe/parametric/reliability data, applying device physics, using AI tools to accelerate learning, managing small projects, and coordinating cross-functional teams with product engineering, TCAD, and process integration to meet performance and reliability targets.

Study photolithography modeling and simulation, develop AI workflows and scripts for OPC and RET tasks, analyze data, improve semiconductor process metrics, document best-known methods, and collaborate with photolithography and technology development engineers.

Supports EUV lithography and semiconductor manufacturing research through experiment design, cleanroom process coordination, metrology and process-data analysis, lithography performance evaluation, and process optimization. Projects may address photoresist performance, critical dimensions, registration, line width roughness, and patterning improvements. The intern communicates technical findings through reports and presentations, collaborates with multidisciplinary engineering teams, and applies AI-assisted tools to research and engineering workflows.

Design and optimize DRAM memory arrays, peripheral logic, and analog circuits. Lead layout, floorplanning, placement, routing, and circuit-level verification. Integrate AI-driven design and automation with CAD/EDA tools, perform parasitic extraction and simulations, and drive methodology improvements for future memory generations.