Top Engineering Jobs

The Staff Engineer - ASIC SOC Verification develops verification plans and test cases using SV, UVM, and interacts with teams to ensure SoC architecture functionality.

Design and deliver full-factory tool layout models for Micron's manufacturing sites (Singapore), establish layout requirements, analyze layout data to recommend improvements, maintain a SharePoint layout repository, collaborate with Technology Development to influence tool designs, present recommendations to senior leadership, and integrate AI-assisted tools and continuous-improvement practices into layout workflows.

Lead sustaining and new-product HBM design work: analyze and resolve silicon issues, implement and verify design updates, drive root-cause analysis, improve yield/reliability, support customer bring-up and system-level debug, and collaborate cross-functionally to improve design and verification methodologies.

Support evaluation, installation, deployment, and improvement of probe FOAK/TOR equipment across sites. Monitor OEE and equipment metrics, troubleshoot probe area issues, support software releases, deploy best-known methods, mentor site teams, evaluate new technologies, and apply AI and data analytics to optimize equipment and processes. Travel as needed and complete projects independently.

Lead wafer probe engineering team to meet quality, output, and cycle-time targets. Optimize probe cards, testers and probers (OEE, UPH, yield), resolve excursions with cross-functional teams, implement SOPs and data-driven continuous improvement, and develop engineering talent and leadership pipeline.

Lead and execute pre-silicon verification for HBM and emerging memory architectures: develop test cases, maintain testbenches, run regressions, analyze coverage, debug full-chip designs, and improve verification methodology in collaboration with global design teams.

The Layout Design engineer will design and develop analog and mixed-signal layouts, perform verification, and manage project timelines. Responsibilities include quality checks and collaboration with global teams.

PhD-level intern will develop and evaluate CMP processes for advanced DRAM, run experiments, apply root-cause analysis and statistical/AI-assisted data analysis, partner with cross-functional teams, and present technical project results.

Lead sustaining HBM design support and end-to-end silicon debug, drive root-cause analysis across DE/PE/TD, improve yield/reliability, support customer bring-up and verification, and implement design updates and automation to enhance product quality.

Lead development, characterization, optimization, and transfer of CMP processes for advanced 3D NAND. Coordinate with global teams and suppliers, run DOE experiments, troubleshoot manufacturing issues, evaluate consumables/hardware, drive process control and yield improvements, and contribute to innovation and documentation.