Top Engineering Jobs

Design and implement complex analog, mixed-signal, and custom digital layout blocks for NAND Flash. Perform floorplanning, placement, routing, parasitic-aware optimization, extraction and validation. Collaborate cross-functionally to ensure manufacturability and performance. Develop automation, scripting and AI-assisted, data-driven layout methodologies and improve layout methodology and documentation.

Lead and manage spares engineering and test-wafer programs in a semiconductor fab. Drive cost, productivity, and quality improvements, optimize test wafer usage, coordinate cross-functional and cross-site stakeholders, perform benchmarking and data-driven analysis, and present status to leadership while ensuring documentation, compliance, and supplier collaboration.

Analyze inline, param, probe, and experiment data to identify and resolve wafer yield issues. Communicate findings to fab process teams, lead multi-area focus teams, publish Pareto yield limiters, support technology transfers, and integrate AI-assisted tools to improve yield and quality.

Lead cross-functional design enablement for DRAM, defining and refining design rules, test structures, APR workflows, and milestones. Coordinate with Design, Process Integration, Product Engineering, and Mask teams to optimize PPAC, evaluate test structures, resolve process/layout issues, and implement GenAI/LLM-compatible workflows for efficiency.

The role involves designing DRAM chip layouts, conducting layout verification, and collaborating globally to meet project schedules while ensuring quality standards.

Responsible for designing, optimizing, and verifying high-speed IO and clocking circuits for DRAM products. Collaborates with teams and analyzes circuit performance.

The Staff Engineer for SSD Validation leads validation and qualification activities for Enterprise and Datacenter NVMe SSDs, oversees testing strategies, and collaborates with various engineering teams to ensure product readiness and quality.

This role involves designing, developing, and optimizing high-speed IO circuits for Micron's DRAM products, ensuring performance evaluation and correlation with silicon results.

Lead development and optimization of advanced wafer-level packaging and stacking equipment. Drive equipment capability, process improvements, cost reduction, and roadmap planning for post-probe wafer/die processing. Collaborate across process, test, product engineering, and quality teams to transition designs from R&D to high-volume production and apply data analysis, SPC/DOE, and automation to improve hardware maturity.

The Layout Design Staff Engineer will create analog and digital block layouts, perform verifications, guide team members, and manage project timelines.