Top Senior Level Perl Jobs
The Firmware Engineer III will design, develop, and modify embedded firmware working collaboratively on various projects for smart home solutions. Responsibilities include R&D, working within an Agile cross-functional team, mentoring junior developers, and resolving product issues throughout different phases of development.
The Sr. DevOps Engineer will build and manage cloud-based infrastructure, develop and maintain CI/CD pipelines, monitor and troubleshoot infrastructure issues, and work collaboratively to ensure scalability, reliability, and security of applications and services. The role emphasizes automation, process monitoring, and the establishment of a safety culture within the DevOps practice.
The Lead DevOps Engineer at Terazo will lead a team in infrastructure upgrades, maintain change management protocols, and enhance production system resiliency. Responsibilities include incident management, promoting best practices, and ensuring compliance with risk management initiatives. The role requires knowledge in automation tools and scripting.
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The Associate Systems Engineer will work within Appian’s Federal Customer Success team, providing technical solutions and support for the Appian platform, including systems administration, scaling applications, and delivering customer-facing solutions. The role also involves mastering a variety of programming and scripting languages and managing cloud-based infrastructures.
The Senior Backend Engineer is responsible for writing server-side code to develop scalable and efficient backend systems. This role involves working with distributed systems, optimizing database queries, and ensuring security in online transactions, while contributing to high-performance gaming experiences.
Lead Database Engineer role at Trusted Concepts division of Two Six Technologies, responsible for designing, implementing, and testing complex data infrastructure. Requires collaboration with various teams and ensuring high-quality solutions. Key responsibilities include network architecture design, continuous improvement recommendations, and technical documentation updates.
The Staff SoC Design Engineer will enhance storage capabilities by developing and optimizing prototype SSD controllers, integrating third-party IP for the HBM memory subsystem, and working closely with verification and physical design teams to ensure timing and functional coverage.
The PHY Design Engineer will design low-power communication systems and develop micro-architecture and SystemVerilog RTL. Responsibilities include collaborating on product specifications, design verification, identifying bottlenecks, and providing guidance to teams on physical design and timing closure.
The Senior Staff RTL Verification Engineer will lead the verification of tag and reader chip designs, develop behavioral models, improve verification coverage, and mentor junior engineers. They will collaborate with cross-functional teams to enhance existing products and participate in developing ultra-low power silicon chips.
Experienced Performance Automation Tester with 8+ years of experience in Test Design, performance diagnostics, performance architecture design, performance tuning, performance monitoring, capacity planning, and software development. Strong expertise in JMeter test scripting and execution for various protocols. Skilled in creating Performance Engineering strategies and assessing non-functional requirements. Proficient in Java/J2EE frameworks and experienced in a Scaled Agile environment.
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