Top Fintech Hardware Engineer Jobs

Design, implement, and deploy ML inference engines on custom FPGA/ASIC hardware. Perform HW/SW co-design with traders and researchers, optimize neural networks for low latency, and build quantization/compression tools to translate ML frameworks to RTL for rapid production deployment.

Design and implement low-latency hardware-based trading solutions while collaborating with traders and engineers to analyze performance and resolve bottlenecks.

As an ASIC Validation Engineer, you'll bridge custom mining silicon design and operation, debugging issues, developing test infrastructure, and validating functionality with ASIC designers.

Lead the development of PMICs, collaborating with multi-disciplinary teams to design algorithms, conduct performance checks, and manage IC design from concept to production.

The Hardware Lab Manager oversees hardware innovation, managing lab operations, performing soldering and rework, and troubleshooting equipment while ensuring efficient workflow and meeting product development milestones.

Lead the integration of sustainability into engineering design decisions, focusing on product-level carbon reduction and sustainable material choices within the transformer business.

The Senior Mechanical Engineer will define product requirements, design mechanical features, develop prototypes, and improve production processes while ensuring compliance with safety standards. Collaborates with cross-functional teams to innovate and manage projects effectively.

The role involves leading engineering efforts, managing teams, designing hardware and software infrastructure, and ensuring compliance with standards while mentoring junior members.

FPGA Engineers at Optiver design and implement low-latency hardware for trading systems, collaborating with software developers and traders to solve complex problems.

As a Senior Hardware Engineer, you'll design and develop low-latency hardware interfaces for financial trading systems, collaborating with software developers and optimizing network communication stacks.