Transistor Reliability and Quality Engineer

Posted Yesterday
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Hillsboro, OR, USA
In-Office
156K-220K Annually
Senior level
Artificial Intelligence • Cloud • Information Technology • Software
Creating world-changing technology that enriches the lives of every person on earth.
The Role
Develops and qualifies transistor reliability for advanced semiconductor process technologies. Responsibilities include reliability characterization, failure and degradation modeling, test-structure and test-chip design, FMEA, statistical analysis, automation, and collaboration with process integration, device, yield, layout, and product teams to support high-volume manufacturing readiness.
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Job Details:

Job Description: 

Intel is seeking a highly motivated and talented Transistor Quality and Reliability Engineer to join our Technology Development Quality and Reliability Engineering team. In this role, you will work at the cutting edge of transistor technology development, ensuring the highest levels of quality and reliability for Intel's next-generation process technologies.
You will collaborate closely with cross-functional teams including Process Integration, Device Engineering, Yield Engineering, and Product teams to drive quality and reliability excellence from early technology development through technology qualification and high-volume manufacturing readiness.
Responsibilities
- Drive transistor reliability characterization and certification activities including but not limited to: Hot Carrier Injection (HCI), Bias Temperature Instability (NBTI/PBTI), Time Dependent Dielectric Breakdown (TDDB)
- Collaborate with process integration and device engineering teams to develop a high volume manufacturable technology that meets yield, performance and reliability requirements.
* Develop FMEA for novel transistor structures and materials
* Define and implement reliability monitors and early warning indicators for technologies
* Drive continuous improvement in reliability methodologies, test structures, and characterization techniques
- Develop physics-based and empirical reliability models for transistor wear-out and degradation mechanisms including:
* Lifetime prediction
* Statistical distribution modeling (Weibull, lognormal)
* SPICE-compatible reliability model development for circuit design enablement
- Design reliability test structures and test-chip layouts to enable:
* Systematic reliability characterization
* Early detection of reliability and quality risks
* Collaboration with layout and design teams to tape-in test-structures and influence design for reliability for partner organizations
- Develop and improve automation framework for data analysis to enable:
* Systematic reliability characterization from a high volume of data across multi variable process modulators

Qualifications:

Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field with 6+ years of industry experience OR a Master's degree in the above fields with 4+ years of experience OR a Ph.D. with 2+ years of experience.

Experience to be considered:
- Hands-on experience in semiconductor device fabrication, process characterization, and experimental design.
- Proficiency in statistical analysis and data interpretation using tools such as JMP, R, SAS, or Python.
- Strong technical background in semiconductor device physics and reliability mechanisms.
- Knowledge of process integration and technology development methodologies.
Preferred Qualifications
- Experience in semiconductor reliability engineering and technology qualification frameworks.
- Familiarity with advanced CMOS process integration and transistor reliability mechanisms (e.g., HTOL, ELFR, TDDB).
- Proficiency in statistical quality systems, process capability analysis, and defect reliability modeling.
- Background in data analytics, machine learning, and AI-assisted engineering workflows.
- Expertise in semiconductor failure analysis, fabrication, and physical characterization techniques.
- Experience with automation and scripting tools such as SQL and Python.
We're looking for exceptional candidates eager to make a lasting impact on Intel's innovation journey. If you're ready to advance groundbreaking technologies and thrive in a collaborative, dynamic environment, we encourage you to take the next step and apply today.

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.



Annual Salary Range for jobs which could be performed in the US: $155,520.00-219,550.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Skills Required

  • Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field with 6+ years of industry experience
  • Master's degree in Electrical Engineering, Materials Science, Physics, or a related field with 4+ years of industry experience
  • Ph.D. in Electrical Engineering, Materials Science, Physics, or a related field with 2+ years of industry experience
  • Hands-on experience in semiconductor device fabrication, process characterization, and experimental design
  • Proficiency in statistical analysis and data interpretation using JMP, R, SAS, or Python
  • Strong technical background in semiconductor device physics and reliability mechanisms
  • Knowledge of process integration and technology development methodologies
  • Experience in semiconductor reliability engineering and technology qualification frameworks
  • Familiarity with advanced CMOS process integration and transistor reliability mechanisms, including HTOL, ELFR, and TDDB
  • Proficiency in statistical quality systems, process capability analysis, and defect reliability modeling
  • Background in data analytics, machine learning, and AI-assisted engineering workflows
  • Expertise in semiconductor failure analysis, fabrication, and physical characterization techniques
  • Experience with automation and scripting tools such as SQL and Python

Intel Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.

  • Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
  • Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
  • Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.

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The Company
HQ: Santa Clara, CA
75,000 Employees
Year Founded: 1968

What We Do

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