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Posted 2 Days Ago
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San Jose, CA, USA
In-Office
Expert/Leader
Big Data • Information Technology
The Role
Design and develop advanced-node CMOS integrated circuit layouts for high-speed analog circuits, including PLLs, DLLs, ADCs, regulators, amplifiers, transmitters, receivers, and CDRs. Responsibilities include floor planning, parasitic and skew reduction, matching, EMIR and antenna compliance, DRC/LVS verification, process yield management, test procedure development, and semiconductor process technology support.
Summary Generated by Built In

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones

As an Integrated Circuit Designer - Layout, you will be part of a key team designing and developing sophisticated advanced node CMOS products.

Key Job Duties:

  • The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS]
  • The management of manufacturing process of the products, including technology yield and performance of the products. 
  • The development of test programmes and procedures to ensure the products meet their performance specifications.
  • The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment.

Basic Qualifications:

  • At least a bachelor’s degree in electrical engineering

Required Experience:

  • 10+ years of experience in the development of layouts for highspeed analog IC designs in fin FET technology.
  • Experience with layout extraction tools and to analyzing layout parasitic to achieve high quality layout for highspeed circuits.
  • EMIR and antenna DRC rules aware layout practices.
  • Experience writing SKILL and TCL scripts is highly recommended

Pay and Benefits



  • Competitive salary.
  • 13th month salary.
  • Performance bonus each year.
  • Long Term Incentive (LTI)
  • Health check each year.
  • Insurance for engineer and family.
  • Lunch Allowance.
  • Company trips.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Skills Required

  • Bachelor's degree in electrical engineering
  • 10+ years of experience developing layouts for high-speed analog IC designs using FinFET technology
  • Experience with layout extraction tools and analyzing layout parasitics for high-speed circuits
  • Knowledge of EMIR and antenna DRC rule-aware layout practices
  • Experience writing SKILL and TCL scripts

Astera Labs Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.

  • Healthcare Strength Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
  • Leave & Time Off Breadth Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
  • Equity Value & Accessibility Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.

Astera Labs Insights

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The Company
HQ: San Jose, CA
148 Employees
Year Founded: 2017

What We Do

Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

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