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The Role
Develops ESD and latch-up reliability solutions and design rules for semiconductor technologies. Designs test structures, plans experiments, performs TLP-based ESD characterization, analyzes test data, and documents findings. Supports test-chip layout, VLSI circuit design, transistor characterization, and ESD modeling. Consults with analog design teams to identify and address ESD risks, while publishing design rules for internal and foundry teams.
Summary Generated by Built In
Job Details:Job Description: The successful candidate will be working in Technology Development ESD, LU reliability engineering group focusing on research and development in Electrostatic Discharge (ESD) and Latch-up reliability area. This position is responsible for developing solutions and design rules to ensure ESD and latch-up reliability in circuits. The engineer will be responsible for but not limited to design test structures, run experiments, analyze data from test structures during technology development phase. ESD characterization on test structures using transmission line pulse (TLP) is required. Responsibilities also include develop, document, and publish design rules to aid internal and foundry design teams. Serve as a consultant to design teams to ensure ESD risks are addressed in analog circuits.Qualifications:
Annual Salary Range for jobs which could be performed in the US: $155,520.00-219,550.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Minimum Qualifications:
- Master's degree in Electrical Engineering, Reliability Engineering, Physics, or related technical field.
- 3+ years experiences in ESD or LU reliability engineering
- 3+ years of experience with Device Physics, device characterization and/or basic VLSI design knowledge
Preferred Qualifications:
- Ph.D. in electrical engineering and 1+ years of experience in ESD, LU reliability engineering
- Experience in planning and guiding the creation of test structure layout on test chips.
- Experience in VLSI circuit design, including analog and digital. Knowledge of state-of-the-art ESD circuit design techniques and topologies.
- Deep understanding of transistor device characteristics and characterization methods.
- Experience with transmission line pulse (TLP) measurement. Experience on ESD models (i.e. CDM, HBM)
- Data analysis background (JMP, Excel) to support design of experiments and analysis.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $155,520.00-219,550.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Master's degree in Electrical Engineering, Reliability Engineering, Physics, or a related technical field
- 3+ years of experience in ESD or latch-up reliability engineering
- 3+ years of experience with device physics, device characterization, and/or basic VLSI design
- Ph.D. in Electrical Engineering
- Experience planning and guiding test structure layout creation on test chips
- Experience in analog and digital VLSI circuit design
- Knowledge of state-of-the-art ESD circuit design techniques and topologies
- Deep understanding of transistor device characteristics and characterization methods
- Experience with transmission line pulse measurement
- Experience with ESD models including CDM and HBM
- Data analysis experience using JMP and Excel
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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The Company
What We Do
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.
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