At the heart of Intel's groundbreaking product advancements, the Logic Technology Development (LTD) organization is a powerhouse of process technology innovation. Our relentless pursuit of excellence and innovation propels Intel's Foundry strategy, ensuring that we not only meet but exceed the aspirations of our global customers. As we continue to lead the semiconductor industry, we are enhancing our technological capabilities to guarantee the triumph of our customers' diverse and ambitious projects.
Your Role in Intel's Foundry Revolution: As a Foundry Technology Development - Staff Yield Engineer, you will be at the forefront of Intel's collaborative journey with our foundry partners. Your expertise will be pivotal in guiding our customers through the intricate journey of product development, starting from testing and validation to New Product Introduction (NPI) phase to the High Volume Manufacturing (HVM). You will play a vital role in overseeing the wafer manufacturing process and ensuring a seamless transition into volume production. This is a unique opportunity to be part of a team that is not just participating in the industry but actively shaping its future.
We are seeking a broad range of semiconductor expertise across the range of foundry technology development.
Based on experience, potential areas may include:
- Serve as the yield point of contact through the cycle of foundry product development, from design to initial High Volume Manufacturing (HVM)
- Define yield goal and roadmap for foundry customer silicon by collaborating with Intel Foundry Services (IFS), Technology Development (TD), and Product Integration
- Collaborate with TD Process Integration, Device, Defect Metro, and Lab to identify yield detractors and yield enhancement opportunities, specifically for foundry customer silicon
- Provide yield / defect density projection for different types of customer silicon, including test chips, shuttles, and products
- Track inline process and non-process changes to incorporate the changepoints into yield prediction model
- Develop yield models to identify potential parametric and defective loss components and support Process Integration, Device and Module teams to develop projects to eliminate systematic yield losses
- Support yield analysis of logic, SRAM, and other types of devices on foundry customer silicon
- Establish correlations between critical inline metrics and yield for better inline control and end of line projection
- Engage side-by-side with Product Integration and Device teams in customer silicon execution, such as skew split planning and DOE
- Lead investigations and root-causing on yield signals for foundry customer silicon
- Identify opportunities to optimize foundry product development operational systems and methodologies to improve efficiency and standardization
- Work as the technical interface between foundry and both internal stakeholders and external customers
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Minimum Qualifications:
- Bachelor’s Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science discipline with 6+ years of relevant work experience
OR
- Master's Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science with 4+ years of relevant work experience
OR
- PhD Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant engineering or physical science discipline with 2+ years of industry experience
The years of relevant work experience listed above must be in the field in at least one of the following areas:
- Semiconductor yield engineering
- Analysis of yield post silicon yield signal and root-causing
Preferred Qualifications:
- 3+ years of semiconductor direct yield analysis and engineering experience
- 3+ direct experience in yield pareto, projection and yield roadmap construction
- 3+ years of experience within a foundry team, or foundry customer yield collaboration
- 3+ years of experience interpreting product data including inline, e-test and SORT data, finding failure root cause and inline indicator and driving for solutions
- Knowledge on inline inspection method, electrical test structures and SORT programs
- Exposure to fabless design house product development
- Foundry customer service experience and evidence of strong customer orientation.
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Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, AustinPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $155,520.00-255,200.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or related plus 6+ years relevant experience
- Master's Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or related plus 4+ years relevant experience
- PhD in Electrical Engineering, Materials Science, Physics, Chemical Engineering or related plus 2+ years industry experience
- Experience in semiconductor yield engineering
- Experience analyzing post-silicon yield signals and performing root-cause analysis
- Direct yield analysis and engineering experience (preferred 3+ years)
- Experience in yield pareto, projection and yield roadmap construction (preferred 3+ years)
- Foundry team or foundry customer yield collaboration experience (preferred 3+ years)
- Experience interpreting inline, e-test and SORT data, and driving failure analysis and solutions (preferred 3+ years)
- Knowledge of inline inspection methods, electrical test structures and SORT programs
- Exposure to fabless design house product development
- Foundry customer service orientation and experience
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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