Technical Program Manager – Hardware/Silicon, Principal

Reposted 8 Days Ago
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Santa Clara, CA
Hybrid
196K-300K Annually
Senior level
Artificial Intelligence • Machine Learning • Software
The Role
The Principal Technical Program Manager will drive engineering excellence in chip development, ensuring predictable project delivery and fostering collaboration between teams.
Summary Generated by Built In

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together, we can help shape the endless possibilities of AI. 

Location:

Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week.

The Role: Principal Technical Program Manager, HW/Silicon

We are seeking a Principal Technical Program Manager to drive engineering excellence across the global hardware organization. This role will focus on creating lightweight, scalable processes that enable predictable project delivery in a high-growth startup environment. You will partner with engineering leaders to translate company objectives into actionable software programs, improve planning and execution practices, and foster collaboration across geographies and technical domains. The ideal candidate should be comfortable working in a fast-paced, globally distributed environment and is passionate about delivering high-quality software on time.

What you will do:

  • Lead end-to-end program management across chip development cycle: feature trade-offs between Product, Architecture, and Design teams; chip architecture, RTL design, design verification, emulation, modeling (power, performance), Design for Test (DFT), Static Timing Analysis (STA), physical design, packaging, analog circuit design, system design and tapeout.

  • Establish well-defined predictable milestones for development within the company and 3rd party partners for IPs, VIPs and physical design.

  • Coordinate delivery across teams in North America and India.

  • Define metrics, create dashboards and reporting to track progress and program health.

  • Develop playbooks and best practices for program management across the organization for cross-functional deliveries.

  • Identify and mitigate risks to delivery schedules and quality.

  • Act as a liaison between hardware teams and company leadership, providing clear updates and insights.

  • Collaborate with Product, Hardware, and other partner teams to manage dependencies.

What you will bring:

Minimum:

  • 10+ years of experience in chip/IC development as an engineer, engineering manager, or technical program manager, with the last 3 or more years as technical program manager.

  • Excellent communication and stakeholder management skills; ability to influence without authority.

  • Experience in companies with complex software/hardware integration.

  • Proven track record managing distributed, multi-region engineering teams.

  • Strong understanding of the chip development cycle and waterfall program management methodologies.

  • Experience establishing scalable processes in fast-moving engineering organizations.

Preferred:

  • Prior industry experience as Engineering Manager responsible for end-to-end chip execution - concept to silicon.

  • Background in datacenter chip development companies.

  • Experience with the latest process technologies and IP/VIP providers.

  • Experience scaling engineering teams at Series B/C stage startups.

  • Proficiency with JIRA, Smartsheet, and project toolchain integration.

  • Experience managing external dependencies and customer-driven timelines.

What we offer:

  • Opportunity to shape program management practices across a fast-growing AI company.

  • High-impact role influencing effectiveness of a global software team.

  • Collaboration with world-class engineers at the cutting edge of AI and system software.

  • Competitive compensation, equity, and professional growth opportunities.

Success Metrics:

  • Predictable release cycles with measurable delivery improvements.

  • More accurate planning and forecasting across projects.

  • Stronger cross-team coordination, measured by stakeholder feedback.

  • Scalable practices supporting growth to 300+ engineers.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Top Skills

JIRA
Project Management Tools
Smartsheet
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The Company
HQ: Santa Clara, CA
102 Employees

What We Do

d-Matrix is building a new way of doing datacenter AI inferencing using in-memory computing (IMC) techniques with chiplet level scale-out interconnects. Founded in 2019, d-Matrix has attacked the physics of memory-compute integration using innovative circuit techniques, ML tools, software and algorithms; solving the memory-compute integration problem, which is the final frontier in AI compute efficiency.

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