Technical Lead Product Engineer

Reposted 3 Days Ago
Be an Early Applicant
San Jose, CA, USA
In-Office
160K-195K Annually
Senior level
Big Data • Information Technology
The Role
Lead the development of high-speed semiconductor products, focusing on post-silicon product development, RF testing, and characterizing advanced semiconductor solutions.
Summary Generated by Built In

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is seeking a Technical Lead Product Engineer to join our team in San Jose, CA. In this role, you will be at the intersection of silicon development and production excellence, ensuring our industry-leading connectivity solutions meet the highest standards of performance, reliability, and quality as they scale to volume production.

The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives. You'll work across the full product lifecycle, partnering with design, applications, and operations teams to drive our connectivity products from tape-out to high-volume manufacturing. This is a high-impact role at a company experiencing explosive growth, where your work directly enables the AI infrastructure revolution.

With Astera Labs' portfolio spanning PCIe retimers, Ethernet solutions, and next-generation switching silicon operating at the bleeding edge of SerDes performance, you'll tackle some of the most demanding high-speed physical layer challenges in the semiconductor industry.

Key Responsibilities

  • Define test coverage strategies that balance quality, cost, and throughput for volume manufacturing
  • Correlate bench characterization results with ATE measurements to ensure production screening effectiveness
  • Partner with OSAT and test vendors to bring up and qualify production test hardware and loadboards
  • Drive silicon qualification and reliability testing to ensure products meet production readiness criteria
  • Drive DFT and design-for-manufacturing improvements based on production test learnings
  • Contribute to product specifications and datasheet development with measured silicon performance data
  • Drive product level decisions in terms of production test coverage, test cost, power and thermal performance

Basic Qualifications

  • Strong academic/technical background in electrical or computer engineering; bachelor’s is required; MS preferred
  • Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed IOs (product, test or validation)
  • Hands-on work with ATE platform including test program updates for wafer sort and final test solutions
  • Have gone through at least one cycle of full product development life cycle
  • Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.
  • Digital and analog circuit level understanding for DUT.
  • Hands-on product/package qualification
  • Excellent team player with great communication skills
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks

Preferred Qualifications

  • Understanding of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), and/or memory interfaces such as (LP)DDR5/4
  • Partnering with Fabs on process development and yield improvement initiatives
  • Collaboration with silicon validation teams to ensure device performance meets production requirements
  • Experience in working with analog high-speed IO testing and characterization
  • Firmware development in C/C++, scripting in Python, or other equivalent programming languages

The salary range for this position is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Skills Required

  • Minimum of 5 years of experience in post silicon product development
  • Experience in RF testing and characterization
  • Knowledge of spectrum analyzers and vector network analyzers
  • Experience with full product development life cycle
  • Strong academic background in electrical or computer engineering
  • Strong problem-solving skills for system level analysis
  • Understanding of digital and analog circuit for DUT
  • Hands-on experience with Advantest 93k ATE platform
  • Strong data analysis skills
  • Energetic work mindset during the manufacturing stage
  • Experience with RF parameter measurements
  • Hands-on product/package qualification
  • Collaboration with silicon validation teams
  • Firmware development in C/C++, scripting in Python

Astera Labs Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.

  • Healthcare Strength Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
  • Leave & Time Off Breadth Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
  • Equity Value & Accessibility Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.

Astera Labs Insights

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The Company
HQ: San Jose, CA
148 Employees
Year Founded: 2017

What We Do

Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

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