Technical Lead - DFT

Posted Yesterday
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2 Locations
In-Office
Senior level
Artificial Intelligence • HR Tech • Professional Services • Software
The Role
Owns DFT for complete SoCs, including architecture, test coverage, power and cost optimization, MBIST, repair, low-power DFT, and STA sign-off. Leads 4–6 engineers, manages schedules and customer reviews, drives tapeout and DFT sign-off, and supports post-silicon ATE bring-up, pattern diagnosis, and yield analysis. Requires 8–9 years of experience and at least five tapeouts, including one as DFT lead.
Summary Generated by Built In

This role is for one of Weekday’s clients

Min Experience: 8+ years
Location: Bengaluru, Noida
JobType: full-time

Own DFT for a full SoC. Derive the DFT architecture with the customer and product engineering teams, lead a team of 4–6 engineers, drive DFT sign-off, and support silicon bring-up.

Experience: 8 to 9 years. Must have 5 or more tapeouts, with at least 1 as DFT lead.


Requirements

Desired Skills:

1. Defines SoC DFT architecture against test time, test cost, coverage, test power and pin budget.

2. Exposure to streaming scan networks (SSN) or tile-based hierarchical DFT for large SoCs.

3. Applies advanced fault models: cell-aware, path delay, small delay defect and IDDQ.

4. Owns SoC-wide MBIST and repair architecture, including shared-bus memory test.

5. Low-power DFT: power-domain aware scan and test-mode power management (UPF-aware DFT).

6. Owns DFT-mode STA sign-off criteria with the STA team.

7. Leads post-silicon work: ATE bring-up, failing-pattern diagnosis and yield diagnosis support.

8. Owns schedule, effort estimates, risk tracking and weekly status to the customer.

9. Leads DFT plan and sign-off reviews, and interviews candidates.

10. LBIST and in-system test for automotive (ISO 26262) is a plus.

Must-have skills

DFT, SoC, tapeout

Good-to-have skills

DFT architecture, streaming scan networks, tile-based hierarchical DFT

Skills Required

  • 8 to 9 years of DFT experience
  • At least 5 tapeouts
  • At least 1 tapeout as DFT lead
  • DFT, SoC, and tapeout experience
  • Experience defining SoC DFT architecture
  • Experience with streaming scan networks or tile-based hierarchical DFT
  • Experience with advanced fault models, including cell-aware, path delay, small delay defect, and IDDQ
  • Experience owning SoC-wide MBIST and repair architecture
  • Experience with low-power, power-domain-aware, and UPF-aware DFT
  • Experience with DFT-mode STA sign-off
  • Experience with ATE bring-up, failing-pattern diagnosis, and yield diagnosis
  • LBIST and in-system automotive testing under ISO 26262
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The Company
HQ: Stockholm
Year Founded: 2021

What We Do

Weekday is an AI-powered recruitment platform that helps startups hire top-tier engineering and product talent. By leveraging a massive database of white-collar professionals and advanced outreach tools, the company streamlines the hiring process through automated sourcing, AI-driven resume screening, and white-glove contingency services. Their mission is to modernize recruitment by enabling companies to discover and engage passive candidates efficiently, ensuring high-quality hires for critical roles.

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