Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
About the Role
We are seeking an experienced AMS (Analog Mixed-Signal) Layout Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm technology node.
In this role, you will be responsible for the layout of advanced analog and mixed-signal circuits, ensuring performance, matching, and manufacturability for high-speed transceiver applications in cutting-edge process nodes.
Key Responsibilities
· Perform full-custom layout of high-speed SerDes design such as RX Front-ends, TX Drivers, PLLs, CDRs, bias circuits, ADCs/DACs.
· Handle layout of high-frequency components with emphasis on parasitic minimization, shielding, and routing symmetry.
· Floorplan and assemble top-level analog/mixed-signal and perform layout integration.
· Work closely with circuit designers to understand schematic intent, matching, symmetry, and parasitic sensitivity.
· Ensure high-quality layout practices to meet DRC, LVS, ERC, and EM/IR signoff in advanced FinFET processes (High-end process nodes).
· Perform layout-versus-schematic (LVS), design rule checks (DRC), and parasitic extraction (PEX) using industry-standard tools (Cadence Virtuoso XL, Calibre ...), .
· Support post-layout simulation by extracting and delivering clean parasitic netlists (RC).
· Collaborate with physical design and digital implementation teams on analog-digital boundary integration.
Required Qualifications
· Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.
· 7+ years of experience in custom analog or mixed-signal layout in deep-submicron or FinFET processes.
· Strong experience with:
o High-speed SerDes designs, PLLs, ADCs/DACs, power management units.
o Handling sensitive matching and noise isolation constraints (e.g., differential pair matching, guard rings).
o Tools like Virtuoso Layout Editor, Calibre, PVS, StarRC, Quantus, or similar.
· Strong understanding of semiconductor physics, CMOS fabrication processes, and advanced process nodes (e.g., 7nm and below).
· In-depth knowledge of layout techniques for minimizing parasitics, noise, and ensuring robust circuit operation.
· Experience with layout debugging and tapeout release process.
Pay and Benefits
· Competitive salary.
· Performance bonus each year.
· Long Term Incentive (LTI)
· Flexible working time.
· Health check each year.
· Insurance for engineer and family.
· Lunch Allowance.
· Company trips
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a related field
- 7+ years of experience in custom analog or mixed-signal layout using deep-submicron or FinFET processes
- Strong experience with high-speed SerDes designs, PLLs, ADCs/DACs, and power management units
- Experience handling sensitive matching and noise-isolation constraints, including differential pair matching and guard rings
- Experience with Virtuoso Layout Editor, Calibre, PVS, StarRC, Quantus, or similar tools
- Strong understanding of semiconductor physics, CMOS fabrication processes, and advanced process nodes such as 7nm and below
- In-depth knowledge of layout techniques for minimizing parasitics and noise and ensuring robust circuit operation
- Experience with layout debugging and tapeout release processes
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
