Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
We are looking for a Analog / Mixed-Signal Layout Engineer to join our ASIC team working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will have an impeccable hardware engineering background with an emphasis on VLSI and/or computer architecture. We are looking for experience in design, verification, and validation of real-world systems. Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies would be great to have. Above all, curiosity and ability to learn is a must. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools.
Basic qualifications:
- Pursuing BS or MS in EE/CS or related fields.
- Hardware engineering background with an emphasis in VLSI or Computer Architecture.
- Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture.
Required experience:
- Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog.
- Familiarity with verification methodologies like UVM, functional coverage, assertions.
- Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C/C++.
Preferred experience:
- Real-world design and/or verification in Verilog/System Verilog.
- Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes.
- Familiarity with Synopsys EDA tools.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Pursuing a BS or MS in Electrical Engineering, Computer Science, or a related field
- Hardware engineering background with emphasis on VLSI or computer architecture
- Exposure to digital design or verification, VLSI design and circuits, and computer architecture
- Hands-on knowledge of RTL design languages and tools, including Verilog and SystemVerilog
- Familiarity with verification methodologies including UVM, functional coverage, and assertions
- Familiarity with scripting languages such as Python or Perl
- Hands-on experience in C or C++
- Real-world design or verification experience in Verilog or SystemVerilog
- Knowledge of high-speed interfaces including PCIe, DDR, HBM, or SerDes
- Familiarity with Synopsys EDA tools
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
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