We are seeking an experienced ASIC Verification Engineer to join our dynamic team. As a verification engineer, you will play a crucial role in ensuring the quality and reliability of our cutting-edge semiconductor designs. If you thrive in a collaborative environment and have a passion for solving complex challenges, this role is for you.
Responsibilities:
- Verification Planning and Execution:
- Develop and execute comprehensive verification plans.
- Close verification with coverage closure, ensuring high-quality results.
- Apply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.
- Testbench Development:
- Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages.
- Implement reusable Verification IP (VIP) components.
- Collaborate with third-party VIP providers.
- Methodology and Flows:
- Demonstrate a solid understanding of ASIC design and verification methodologies.
- Apply object-oriented programming principles effectively.
- Implement constraint random verification methodology.
- Technical Skills:
- Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI).
- Familiarity with industry standards (e.g., I2C/SPI).
- Experience with low-power verification using UPF (Unified Power Format) is a plus.
- Knowledge of formal verification techniques is advantageous.
- Collaboration and Communication:
- Work effectively with internal teams and external customers.
- Strong written and verbal communication skills.
- Initiative, analytical problem-solving abilities, and adaptability within a diverse team environment.
#LI-RG1
ResponsibilitiesWe are seeking an experienced ASIC Verification Engineer to join our dynamic team. As a verification engineer, you will play a crucial role in ensuring the quality and reliability of our cutting-edge semiconductor designs. If you thrive in a collaborative environment and have a passion for solving complex challenges, this role is for you.
Responsibilities:
- Verification Planning and Execution:
- Develop and execute comprehensive verification plans.
- Close verification with coverage closure, ensuring high-quality results.
- Apply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.
- Testbench Development:
- Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages.
- Implement reusable Verification IP (VIP) components.
- Collaborate with third-party VIP providers.
- Methodology and Flows:
- Demonstrate a solid understanding of ASIC design and verification methodologies.
- Apply object-oriented programming principles effectively.
- Implement constraint random verification methodology.
- Technical Skills:
- Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI).
- Familiarity with industry standards (e.g., I2C/SPI).
- Experience with low-power verification using UPF (Unified Power Format) is a plus.
- Knowledge of formal verification techniques is advantageous.
- Collaboration and Communication:
- Work effectively with internal teams and external customers.
- Strong written and verbal communication skills.
- Initiative, analytical problem-solving abilities, and adaptability within a diverse team environment.
#LI-RG1
Qualifications- Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or related fields.
- 7 Years experience in design verification using SV/UVM based test-benches
- Proven track record in complex ASIC verification.
- Passion for solving challenging problems and ensuring product reliability.
#LI-RG1
About UsMore details about our company benefits can be found here:
https://www.onsemi.com/careers/career-benefits
Skills Required
- Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or related fields
- 7 Years experience in design verification using SV/UVM based test-benches
- Proven track record in complex ASIC verification
onsemi Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about onsemi and has not been reviewed or approved by onsemi.
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Retirement Support — Retirement programs are highlighted by a U.S. 401(k) with a 100% match on the first 4% and immediate vesting. International plans such as Ireland’s defined contribution scheme and Germany’s company-funded pension elements reinforce long-term savings.
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Leave & Time Off Breadth — Time-off policies include ten paid holidays, flexible vacation for exempt employees, and three to five weeks of vacation for non-exempt staff as tenure grows, alongside sick time accrual. Paid leaves span parental, bereavement, jury duty, and military service, with Europe locations offering additional statutory and seniority-based days.
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Parental & Family Support — Family supports include eight weeks of paid parental leave, company-sponsored backup care for children, adults, and pets, and up to $15,000 in adoption assistance. Regional provisions such as Switzerland’s child allowance and accessible EAP counseling show added attention to household needs.
onsemi Insights
What We Do
We are building a better future through intelligent technology. For over 60 years, onsemi and its ancestors have been leading the world’s greatest technology advancements. onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
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