As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
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To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
About the Role:
SiFive is looking for a Staff Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs. In this role, you will own complex verification problems spanning coherent data movement, protocol correctness, ordering, quality-of-service behavior, and subsystem integration across multiple interface types. The scope aligns to the Interconnect horizontal area and the coherent interconnect subsystem, with adjacent responsibilities around protocol conversion, bridges, and integration behavior.
This is a Staff individual-contributor role. We are looking for someone who can go beyond executing assigned tests and instead define strategy, identify gaps early, solve complex verification problems, and raise the quality bar for the broader verification effort.
Responsibilities
Own verification planning and execution for a scalable cache-coherent interconnect subsystem, from block-level verification through subsystem integration.
Develop and maintain robust verification environments, checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, and error handling.
Verify protocol adaptation and integration across multiple interface types and bridge paths, including conversion, buffering, deinterleaving, and related data movement behaviors.
Drive verification of advanced interconnect behaviors such as QoS handling, arbitration policy, virtual-network behavior, and transport-level correctness.
Define high-value directed and constrained-random test scenarios that expose corner cases in coherency, concurrency, ordering, credits, and integration.
Partner closely with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff.
Analyze failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
Improve verification methodology, infrastructure, and productivity for the broader interconnect verification effort, not just the block immediately assigned to you.
Contribute to review quality across specs, verification plans, coverage closure, and debug strategy.
Minimum Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
7+ years of experience in ASIC or SoC design verification.
Strong hands-on experience with SystemVerilog and UVM-based verification.
Strong understanding of cache-coherent systems, on-chip interconnects, or memory-system verification.
Experience verifying complex protocol behavior such as ordering, flow control, backpressure, buffering, arbitration, and error handling.
Experience building reusable testbench components, assertions, coverage models, and debug infrastructure.
Strong debugging skills and ability to root-cause issues across specification, RTL, and testbench layers.
Ability to work effectively across architecture, design, and verification teams in a fast-moving environment.
Preferred Qualifications
Experience with coherent interconnects, NoCs, memory fabrics, or large subsystem integration.
Experience with one or more industry protocols such as AXI, CHI, CXL, UCIe, or similar high-performance interface standards.
Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug.
Experience verifying protocol-conversion or bridge-heavy subsystems.
Familiarity with Python or other scripting languages used for DV infrastructure and automation.
Experience mentoring other engineers and raising team-wide verification quality.
What Success Looks Like
Verification plans are complete, concrete, and aligned to the real architectural risks.
Critical bugs are found early, reproduced efficiently, and closed with durable fixes.
Coverage and test quality improve meaningfully under your ownership.
The coherent interconnect verification effort becomes more scalable, predictable, and reusable because of your contributions.
Design and architecture teams rely on you as a strong technical partner for difficult verification and debug problems.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Skills Required
- 7+ years of experience with BS/MS in Electrical Engineering, Computer Engineering, or related field
- Strong experience in formal verification of RTL designs
- Solid knowledge of SystemVerilog and SVA
- Experience verifying interconnects, NoCs, coherent fabrics, or complex SoC subsystems
- Good understanding of NoC building blocks such as arbiters, routers, crossbars, flow control, buffering, and protocol adapters
- Experience with debugging formal failures, constraint issues, and proof complexity
- Strong problem-solving and communication skills
- Experience with coherent interconnect protocols and memory subsystem verification
- Experience with performance-oriented verification, simulation, or emulation
- Familiarity with clock-domain crossing, reset verification, deadlock/livelock checks, and end-to-end data integrity properties
- Scripting experience in Python, Perl, or Tcl for automation and flow improvements
- Experience defining verification strategy and signoff criteria for complex IP/subsystems
What We Do
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
