Staff Engineer, Digital Verification

At Butterfly Network, we’re leading a digital revolution in medical imaging, transforming an industry that has long relied on bulky, analog systems. With our proprietary Ultrasound-on-Chip™ technology, we’re democratizing healthcare by shifting ultrasound from the expensive, stationary systems of the past to the connected, mobile, and software-enabled platforms of today.  In 2018, we launched the world’s first handheld, whole-body ultrasound, Butterfly iQ – followed by iQ+ in 2020 and iQ3 in 2024, each more powerful than the last.

Our innovation doesn’t stop at hardware. Butterfly combines our advanced device with intelligent software, AI, services, and education to drive adoption of affordable, accessible imaging. Our technology is proving to help clinicians, clinics, and hospitals enhance care, cut costs, and expand imaging access. We’ve been recognized by Prix Galien USA, Fierce 50, TIME’s Best Inventions, Fast Company’s World Changing Ideas, among other awards.

We’re a team of bold thinkers, problem-solvers, and innovators ready to shape the future of medical imaging. Let’s build something extraordinary together!

The role of the Staff Digital Verification Engineer offers the opportunity to work at the core of the product development team alongside company leadership and founders, helping ensure the correctness and robustness of the digital systems that differentiate Butterfly Network’s products. This individual will be responsible for architecting, developing, and executing comprehensive verification strategies for complex digital signal processing blocks, high-speed interfaces, and large system-on-chip (SoC) designs used in next-generation ultrasound imaging platforms.

As a senior member of the engineering team, you will drive verification methodology, automation, and infrastructure to enable rapid development and high confidence in silicon correctness.

As part of our team, your core responsibilities will include:

• Architect and develop verification environments for large SoC subsystems using Python-based frameworks, primarily Cocotb.
• Design and implement self-checking testbenches, constrained stimulus, scoreboards, and coverage infrastructure.
• Develop bit-accurate reference models (Python) to validate DSP and fixed-point behavior.
• Verify complex digital signal processing blocks, high-speed interfaces, and system-level datapaths.
• Collaborate closely with RTL designers to define verification plans, drive coverage closure, and ensure design correctness.
  Develop and maintain automated regression infrastructure and CI pipelines using GitHub-based workflows.
• Debug functional issues in simulation, emulation, and post-silicon environments.
• Contribute to improving the verification methodology, productivity tools, and infrastructure used across the team.
• Work cross-functionally with architecture, RTL design, firmware, and system teams to ensure robust end-to-end functionality.

• BS/MS/PhD in EE/CE (or equivalent practical experience in digital verification).
• 8+ years (typical Staff level) experience in digital IC / ASIC / SoC verification.
• Strong experience building and maintaining Python-based verification environments, particularly Cocotb.
• Deep knowledge of SystemVerilog and digital design concepts sufficient to effectively verify complex RTL.
• Proven experience verifying large digital IP blocks or SoC subsystems through full verification closure and tapeout cycles.
• Experience building self-checking testbenches, scoreboards, monitors, and stimulus generators.
• Experience developing bit-accurate Python models for algorithm verification and golden reference comparison.
• Strong debugging skills across simulation, waveform analysis, and root-cause analysis of RTL issues.
• Experience building automated regression frameworks and CI workflows using GitHub or similar tools.
• Solid understanding of SoC design challenges including CDC/RDC verification, reset architecture, and power-aware verification.
• Strong cross-functional communication skills working with RTL designers, architecture teams, and firmware engineers.

• Experience verifying compute-intensive DSP pipelines (e.g., beamforming, filtering, MAC-heavy datapaths).
  Familiarity with ultrasound or medical imaging signal processing pipelines.
  Experience verifying high-bandwidth streaming architectures and large on-chip data pipelines.
• Exposure to advanced node SoCs (28nm or below).
• Experience integrating and verifying embedded processors or accelerator subsystems.
  Experience with ECO or system-level validation flows.

Innovation is what we do. Our values are how we make it happen. Butterflies are and believe in…

• Patient-Centric Innovators: Our mission is THE mission.
• Empowered to Impact: Every voice matters.
• One Team, One Goal: Unity fuels progress.
• Growth Champions: We embrace challenges.
• Action-Oriented Achievers: We follow through, every time.

Butterfly offers a hybrid work model for most positions, with team members spending two or more days a week in the office. While flexibility is key, we value in-person connections that spark creativity and teamwork. Our offices are designed for collaboration, with comfortable workspaces, stocked kitchens, and opportunities to connect with peers.

This is a hybrid position and will be based out of our office in either the Greater SF Bay Area or  Burlington, MA. 

• Comprehensive health insurance, encompassing dental and vision coverage, is provided to all our employees. As a health-tech company, we prioritize the well-being of our teams. We also contribute to Health Savings Account (HSA) accounts for all enrolled employees on an annual basis.
• Comprehensive Employee Assistance Program - we provide access to tools and resources to support your emotional health and day-to-day needs.
• 401k plan and match - we facilitate your retirement goals.
• Eligible employees will have the opportunity to participate in Employee Stock Purchase Plan (ESPP)
• Unlimited Paid Time Off + 10 Holiday Days a Year - recharge and come back ready to make an impact
• Parental Leave - we aim to provide our employees with time to bond with their growing family, along with additional support for primary caregivers to help transition back to work 
• Competitive salaried compensation - we value our employees and show it 
• Equity - we want every employee to be a stakeholder
• The opportunity to build a revolutionary healthcare product and save millions of lives! 

Our Estimated salary for this role located in Burlington, MA is around $175, 000, along with bonus, equity, and comprehensive benefits. Compensation is determined based on skills, qualifications, experience, and market demand.

Our Estimated salary for this role located in the SF Bay Area is around $200,000, along with bonus, equity, and comprehensive benefits. Compensation is determined based on skills, qualifications, experience, and market demand.

For this role, we are only considering candidates who are legally authorized to work in the United States and who do not now or in the future require sponsorship for employment visa status.

Butterfly Network does not accept agency resumes.

Butterfly Network is an E-Verify Company. 

Butterfly Network is an equal opportunity employer.  Regardless of race, traits associated with race, color, ancestry, religion, gender, national origin, sexual orientation, age, citizenship, marital status, disability or Veteran status. All your information will be kept confidential according to EEO guidelines.

Butterfly requires security adherence responsibilities from all employees. These include:  adhering to all company security policies and procedures, utilizing provided company assets securely, and completing all required security awareness training programs. Safeguarding company data and systems from unauthorized access, modification, or destruction, contributing to the overall security posture of the organization. Immediately reporting any suspected or actual security incidents, including phishing attempts, malware infections, or unauthorized access, following the established incident response procedure

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