Staff Engineer - ASIC SOC Verification

This role is for one of Weekday’s clients
Salary range: Rs 1000000 - Rs 9000000 (ie INR 10 - 90 LPA)

Min Experience: 7+ years
Location: Bengaluru
JobType: full-time

We are seeking an experienced Staff Engineer – ASIC SOC Verification with 7–18 years of experience in semiconductor design and verification. The ideal candidate will have strong expertise in SoC verification, with a proven ability to develop comprehensive verification strategies, build robust verification environments, debug complex issues, and deliver high-quality silicon-ready designs.

As a Staff Engineer, you will work closely with RTL design, architecture, firmware, emulation, physical design, and validation teams to verify complex SoC designs across multiple levels of integration. You will contribute to verification planning, methodology development, execution, and sign-off while providing technical leadership on challenging verification problems.

• Own and drive verification activities for complex ASIC/SoC designs from verification planning through final sign-off.
• Develop detailed verification plans based on architecture and design specifications, ensuring comprehensive functional and corner-case coverage.
• Design, develop, and maintain scalable verification environments using industry-standard methodologies.
• Create and enhance SystemVerilog/UVM-based testbenches, test cases, sequences, scoreboards, monitors, drivers, and functional coverage models.
• Develop constrained-random and directed tests to validate complex SoC functionality and system-level interactions.
• Perform functional, block-level, subsystem, and full-chip verification.
• Analyze simulation failures, debug complex RTL/testbench issues, and work closely with design teams to identify and resolve root causes.
• Drive coverage closure, including functional and code coverage, and identify verification gaps.
• Participate in regression planning and execution, improving automation, test efficiency, and verification quality.
• Review specifications, RTL, verification environments, and test plans to identify potential design and verification risks.
• Collaborate with architects, RTL designers, firmware engineers, emulation teams, and post-silicon validation teams.
• Mentor junior and senior verification engineers and provide technical guidance on verification methodologies and best practices.
• Contribute to improving verification flows, reusable components, automation frameworks, and engineering processes.

• 7–18 years of hands-on experience in ASIC/SoC verification.
• Strong expertise in Verification of complex digital ASICs and SoCs.
• Excellent knowledge of SystemVerilog and UVM.
• Strong understanding of verification methodologies, testbench architecture, constrained-random verification, assertions, functional coverage, and coverage closure.
• Experience developing reusable verification components and scalable verification environments.
• Strong debugging skills across RTL, testbench, simulation, and regression failures.
• Proficiency with simulation and verification tools such as VCS, Questa/ModelSim, or equivalent.
• Strong understanding of digital design concepts, RTL, computer architecture, and SoC-level integration.
• Experience working with complex interfaces and protocols such as AMBA AXI/AHB/APB, PCIe, DDR, Ethernet, or similar is desirable.
• Strong scripting/programming skills in Python, Perl, Tcl, or C/C++ for verification automation.
• Ability to independently own verification deliverables and work effectively across multidisciplinary engineering teams.

• Experience with formal verification, emulation, FPGA prototyping, or post-silicon validation.
• Exposure to low-power verification, CDC/RDC, performance verification, or safety/security verification.
• Experience contributing to multiple tape-outs or production SoC programs.
• Strong technical leadership, problem-solving, communication, and mentoring skills.