Staff DFT Engineer

Posted Yesterday
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Austin, TX, USA
Hybrid
198K-268K Annually
Expert/Leader
Artificial Intelligence • Internet of Things • Semiconductor
Build What the World Depends On
The Role
Architects, implements, and validates design-for-test techniques for Arm SoCs and subsystems. Responsibilities include DFT insertion, RTL and gate-level simulation, ATPG pattern generation, coverage debugging, DFT timing analysis, scan insertion, timing closure, ATE test validation, silicon debug, and characterization. The role collaborates with RTL, verification, physical implementation, test, and product engineering teams throughout development and tape-out.
Summary Generated by Built In
Arm's Solutions group DFT team implements DFT for SOC for client, datacenter, automotive, and IOT line of business using the latest DFT and process technologies. We closely collaborate with Arm's partners and internal RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.
We are hiring in San Jose and Austin.
Responsibilities:
  • Architect, implement, and validate innovative DFT techniques on SOCs and sub-systems!
  • Insert DFT logic into SoC as well as sub-system level and validate all DFT features using industry standard simulation tools.
  • Run RTL and well as unit delay and timing annotated gate level simulations
  • Generate ATPG patterns and debug coverage issues to meet target
  • Develop and validate design-for-test timing requirements, review timing reports and provide fixes.
  • Collaborate with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
  • Participate in ATE targeted test patterns, validation and silicon- debug
  • Collaborate with Test and product engineering teams on silicon characterization and validation!

Required Skills and Experience :
  • Bachelors or Master's degree in Electronic Engineering, Computer Engineering, or a related field.
  • This role is for a Staff DFT Engineer with 10+ years of experience in Design for Test
  • Core DFT skills considered crucial for this position should include some of the following: Siemens DFT tools, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics.
  • Experience coding Verilog RTL, TCL and/or Perl.
  • Experience with Cadence, and/or Synopsys DFT and simulation tools.

"Nice To Have" Skills and Experience :
  • Familiarity with SoC style architectures including multi-clock domain and low power build practices.
  • Familiarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug
  • Background in high performance build, implementation and DFT timing constraints is a huge plus
  • Experience in datacenter chips is plus
  • Experience with 2.5D and 3D test
  • Ability to work both collaboratively on a team and independently.
  • Innovative and a passion for progress
  • Hard-working and excellent time management skills with an ability to multi-task
  • An upbeat approach to working on exciting projects on the cutting edge of technology
  • Communicate optimally across teams and sites in different geographies and time zones

Salary Range:
$198,100-$268,000 per year
We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process.
Accommodations at Arm
At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [email protected] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.
Hybrid Working at Arm
Arm's approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team's needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.
Equal Opportunities at Arm
Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don't discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Skills Required

  • Bachelor’s or master’s degree in electronic engineering, computer engineering, or a related field
  • 10+ years of experience in design for test
  • Experience with Siemens DFT tools
  • Experience with Streaming Scan Network, scan compression and insertion, Memory BIST and repair, Logic BIST, JTAG/IJTAG, at-speed testing, ATPG, fault simulation, gate-level verification, silicon debug, and memory and scan diagnostics
  • Experience coding Verilog RTL, Tcl, and/or Perl
  • Experience with Cadence and/or Synopsys DFT and simulation tools
  • Familiarity with SoC architectures, multi-clock domains, and low-power design practices
  • Familiarity with Arm IP, including Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, and CoreSight debug
  • Experience with high-performance implementation and DFT timing constraints
  • Experience with datacenter chips and 2.5D or 3D test
  • Ability to collaborate independently and across teams, communicate across geographies, manage multiple tasks, and work effectively in a fast-paced environment
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The Company
HQ: Cambridge, England
8,314 Employees
Year Founded: 1990

What We Do

We bring brilliant people together in a global ecosystem that is sparking the world’s potential. Arm technology enables specialized processing built on the economics, design freedom and accessibility of general-purpose compute that has, so far, led to more than 180 billion chips being shipped by our partners.

Why Work With Us

At Arm, we build the future of computing, powering everything from smartphones to AI. Our 10x mindset drives bold thinking and deep collaboration to solve complex problems together. With a people first culture, flexible work, and strong support for growth and wellbeing, your ideas can make a global impact while your career thrives.

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