Staff Design Verification Engineer

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

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Job Description:

As a Staff Hardware Engineer in Design Verification, you will own verification strategy and execution for complex out‑of‑order (OOO) processor and cache/memory subsystems. You will define methodology, lead testplan creation, and drive verification of speculative execution, memory ordering, and coherence features from architecture through tape‑out.

Verification Ownership

• Own verification of OOO core subsystems, e.g.:

  • Front‑end: fetch, branch prediction, instruction decode, rename.

  • Back‑end: scheduler/issue queues, execution units, bypass networks.

  • Retirement & recovery: ROB, commit, exceptions, interrupts, mispredict recovery.

  • Memory subsystem: LSU, TLBs, MMU, L1/L2 caches, coherence, fences, atomics.

• Define verification strategy and test plans from ISA + micro‑architecture specs, with emphasis on:

  • Speculative execution, forwarding, hazards, and replay mechanisms.

  • Memory consistency model (e.g. RVWMO, TSO) and ordering rules.

  • Coherence/consistency interactions across multi‑core systems.

• Drive coverage closure (functional, code, assertion, and scenario coverage) to sign‑off criteria.

Testbench Architecture & Implementation

• Architect constrained‑random, coverage‑driven UVM testbenches for:

  • OOO core pipeline (including scoreboards and scoreboard‑driven checking).

  • Cache/memory hierarchy, TLB/IOMMU, and coherence protocols.

• Develop reusable verification components: generators for OOO stress (back‑to‑back branches, deep speculation, dependency patterns), monitors, scoreboards, and protocol checkers.

• Model reference behavior (ISA / memory model) for end‑to‑end checking of:

  • Instruction retirement,

  • Register and memory architectural state,

  • Fence and atomic semantics.

Formal & Assertion‑based Verification

• Write and maintain assertions for key OOO properties, e.g.:

  • No deadlock or livelock in issue/ROB/LSU.

  • Correct flush/replay on branch mispredict, exception, and interrupt.

  • Load‑store ordering and data‑bypass correctness.

• Apply formal verification to targeted units (e.g. ROB, scoreboard, arbiters, FIFOs, coherence controllers, TLB state machines).

Debug & Quality

• Lead debug of complex OOO bugs:

  • Subtle ordering violations, rare hazards, corner‑case speculation issues.

  • Coherence races, TLB edge cases, and PMP/privilege interactions.

• Work closely with RTL, micro‑architecture, and performance teams to root‑cause issues and refine designs.

Methodology, Infrastructure, and Leadership

• Evolve DV methodology to efficiently cover OOO behavior:

  • Scenario libraries for stress (long dependency chains, mixed privilege, multi‑thread/multi‑core).

  • Memory model and coherence checkers integrated into the environment.

• Mentor junior DV engineers on OOO CPU verification, debug strategies, and best practices.

• Collaborate cross‑functionally with architecture, design, SW, and post‑silicon teams to ensure end‑to‑end coverage of CPU use‑cases and customer workloads.

Required Qualifications:

Education / Experience

• BS/MS/PhD in EE/CE/CS or related field.

• Typically 8+ years in ASIC/SoC/IP design verification, with significant experience on out‑of‑order CPU or advanced core projects.

Technical Skills

• Strong expertise in System Verilog and UVM.

• Direct verification experience with OOO CPU micro‑architecture, including several of:

  • Instruction fetch, decode, rename, and register mapping.

  • Issue queue / scheduler, physical register files, bypass networks.

  • Reorder buffer, exception/interrupt handling, flush/replay.

  • Load‑store unit, store buffer, speculative loads/stores, LR/SC and atomics.

  • TLBs, MMU, page table walkers, and protection (e.g. PMP, virtual memory).

• Solid understanding of:

  • Memory consistency models (e.g. RVWMO, TSO) and how they map onto hardware.

  • Coherence protocols and cache hierarchy (L1/L2+, inclusive/exclusive, write‑back).

• Hands‑on experience with:

  • Coverage‑driven verification and coverage closure.

  • Assertion‑based verification (SVA).

  • Debug tools and large‑scale regression environments.

Preferred / Nice‑to‑Have:

• Experience verifying multi‑core OOO systems and inter‑core coherence.

• Experience with formal verification of OOO structures (e.g. scoreboard, ROB, load‑store queues).

• Exposure to RISC‑V or ARM ISA and privilege specs, including virtualization and security extensions.

• Experience with performance verification or micro‑architectural modeling (to cross‑check pipeline behavior).

• Proven track record of technical leadership on complex CPU or SoC projects (tape‑outs, methodology ownership, cross‑team initiatives).

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.