The demand for new datacenters and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn’t about bigger chips or more of them; it means rethinking the fundamental architecture. The industry's current path isn’t going to meet the need, so we took a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.
Join us and shape the future of computing!
Position OverviewWe are seeking a seasoned Senior or Staff Analog Layout Engineer to play a vital role in developing cutting-edge full-custom electronic transceiver components that interface directly with our custom silicon photonics and are essential to our revolutionary photonic AI platform. You will develop and optimize high-performance Analog IPs tailored for TSMC’s deep-submicron processes, including N12, N3P, and N2P. You will push the boundaries of Power, Performance, and Area (PPA) while mitigating the impact of Restricted Design Rules (RDRs) and electromigration.
San Jose, CA or Hsinchu, Taiwan. Full-time onsite position.
Key ResponsibilitiesPerform custom IC layout execution of high-speed analog/RF circuits.
Optimize layout solutions to meet stringent TSMC manufacturing constraints, DFM rules, and antenna restrictions
Deliver IP-level floor planning, power planning, and signal distribution, implementing layout techniques for strict ESD and Latch-up prevention.
Execute and debug block-level design sign-offs, including DRC (Design Rule Check), LVS (Layout Versus Schematic), and RC Extraction using standard industry tools.
Evaluate layout trade-offs among area, yield, and performance; implement the power and clock delivery networks to ensure power and signal integrity.
Coordinate directly with circuit designers, CAD engineers, and EDA vendors to ensure IP design fits seamlessly into the production flow.
B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a closely related discipline.
3-8+ years of professional custom or block-level IC layout experience in deep-submicron, advanced FinFET/GAA nodes (3nm, 2nm, etc.).
Mastery of industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV).
Deep understanding of deep-submicron layout techniques, parasitic reduction, matching strategies, and electro-migration (EM/IR).
Prior tape-out success in TSMC N3 or N2 process nodes.
Domain knowledge in laying out high-performance analog/mixed signal blocks, such as PLLs and Data Converters (ADC/DAC).
Working knowledge of layout automation scripting languages (e.g., TCL, Perl, Python).
This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on a game-changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.
BenefitsJoin a team that invests in your future and your well-being. At Neurophos, we offer:
100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
Unlimited PTO. No rigid vacation banks, just a focus on delivery.
401(k) matching and stock option opportunities to ensure our success is your success.
Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.
Skills Required
- B.S. or M.S. degree in Electrical Engineering or related discipline
- 3-8+ years of professional custom or block-level IC layout experience
- Mastery of industry-standard EDA tools for layout and verification
- Deep understanding of deep-submicron layout techniques
Neurophos Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Neurophos and has not been reviewed or approved by Neurophos.
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Healthcare Strength — Job postings indicate the company covers 100% of base health plan premiums for employees and dependents and contributes to HSAs. Listings also reference dental, vision, and other voluntary coverages.
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Leave & Time Off Breadth — Unlimited PTO is advertised with an emphasis on delivery rather than accruals. Notes in postings suggest clarifying typical usage and any minimums.
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Retirement Support — A 401(k) with employer matching is listed alongside stock option opportunities. This pairing signals structured retirement support in addition to equity participation.
Neurophos Insights
What We Do
Neurophos is an Austin-based semiconductor company developing high-performance, energy-efficient photonic AI inference chips. Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density for an optical system. As AI adoption accelerates, data centers face significant power and scalability challenges. Traditional solutions are struggling to keep up, leading to rapidly rising energy consumption and costs. We’re solving both problems with an OPU that integrates over one million micron-scale optical processing components on a single chip. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving large-scale AI inference performance. We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years. Join us and shape the future of optical computing!
Why Work With Us
This is an opportunity to work on a game-changing technology at the intersection of photonics and AI. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence.
