Responsibilities:
Analog block or analog system design, from specification definition, high-level analysis, detailed transistor-level design, simulation, optimization, test to support to production. (40%)
Design & optimization, verification, technical documentation, layout supervision. (20%)
Silicon lab evaluation, characterization and debug. (10%)
Block or system modelling. (10%)
Technical support to test, product and application engineers. (10%)
Interface with digital, firmware, verification, layout and cross functional teams. (10%)
Minimum Qualifications:
3+ years' experience in analog CMOS integrated circuit design
M.S. in EE or higher
Strong analytical, synthesis and problem solving skills
Solid understanding and experience in designing transistor-level CMOS analog blocks and systems, including IC technology and layout, with blocks such as ADCs, DACs, sensor interfaces, switched-capacitor blocks, power management, LDO regulators, bandgap, biasing circuits, amplifiers, oscillators, PLLs, comparators, filters, physical IOs etc.
Strong knowledge of analog concepts, techniques and trade-offs like speed, power, noise, mismatch, linearity, stability, area
Mastering of IC design CAD tools including schematic entry, Spice and mixed-mode simulation tools
Experience with lab instruments (e.g. oscilloscopes, supplies, meters) and the associated measurement methods
Independent, self-motivated, rigorous, team player and able to follow through
Excellent verbal and written communication skills
Desired Qualifications
Knowledge of system-level aspects: signal processing, digital, modelling, test and application
Experience with mixed-signal circuits, high-resolution & low-power analog design and techniques
Experience with Cadence Virtuoso, Spectre/AFS, Siemens Symphony, Matlab, Verilog/VHDL etc.
Experience with analog/mixed-signal behavioral model development/verification
Experience with consumer and/or ITA market circuit developments
Skills Required
- 3+ years' experience in analog CMOS integrated circuit design
- M.S. in EE or higher
- Solid understanding and experience in designing transistor-level CMOS analog blocks
- Mastering of IC design CAD tools
- Experience with lab instruments and measurement methods
Semtech Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Semtech and has not been reviewed or approved by Semtech.
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Parental & Family Support — Up to 20 weeks of paid maternity/parental leave is highlighted in multiple regions. Enhanced leave is positioned as a core part of the package.
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Healthcare Strength — Medical, dental, and vision coverage are standard elements of the offering. Core health coverage features prominently alongside other benefits.
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Leave & Time Off Breadth — Paid vacation and time‑off programs are explicitly included. Time off is emphasized together with flexible/hybrid work policies where possible.
Semtech Insights
What We Do
Semtech Corporation is a high-performance semiconductor, IoT systems and Cloud connectivity service provider dedicated to delivering high quality technology solutions that enable a smarter, more connected and sustainable planet.
