Sr Staff Package Design Engineer

Posted 4 Days Ago
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Tempe, AZ, USA
In-Office
Senior level
3D Printing
The Role
Lead design and development of advanced package and interconnect methods for power SiP/modules, WLCSP, flip-chip LGA and multi-chip modules. Drive wafer-level processes (Cu RDL, thinning, backside metal), define substrate and interconnect requirements, qualify materials and OSAT/CM processes, run DOE and SPC, resolve process integration issues, and support production ramp and quality for consumer, industrial, and automotive power applications.
Summary Generated by Built In
Job Description

  • Design and develop package and interconnect methods for Renesas’s packaging needs in the areas of Power SiP/modules, WLCSP, multi-chip module with substrate or embedded die/capacitor and power device packaging.
  • Develop Cu RDL with seed layer on IC wafer and FET and Backside metal deposit after grinding
  • Wafer thinning development through Taiko BG and Glass carrier bond
  • Define substrate, die interconnection through via, materials and PCB interface requirements
  • Package technologies qualification for consumer & industrial power as well as automotive power applications.
  • Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).
  •  Work with OSAT/CM to develop, run DOE to optimize processes and establish process spec.
  • Work with Product groups and Reliability team, qualify new packages and processes within required time frame.
  • Resolve all process integration issues by ensuring all window checks are done on critical process steps.
  • Establish production controls and monitor to ensure there is no room for quality incidents.
  • Ensure smooth transition into production & implement ramp up monitor.
  • Work with OSAT/CM to monitor and resolve process issues early in the production stage to ensure only parts with superior quality shipped to customer.
  • Develop and maintain technical expertise on advances and innovations in power SiP/modules, wafer level packaging & flip chip interconnects in LGA.
  • Participate in packaging roadmap development & focus on execution.
  • Address internal and external customer complains working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses.
  • Establish & maintain package design rules

Qualifications

  • Doctorate/Masters / Bachelor’s Degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.
  • 10-15 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip LGA packaging.
  • Strong understanding of power SiP/modules which has an substrate or embedded die/capacitor, assembly process knowledge, qualification methods, SPC and statistical analysis software. Knowledge of Cu FSM/BGBM technologies a plus.
  • Strong interpersonal and communication skills.
  • Strong analytical and presentation skills.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.

Skills Required

  • Doctorate, Masters, or Bachelor's in Physics, Chemistry, Mechanical, Electrical or Materials Engineering
  • 10-15 years relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip LGA packaging
  • Experience with substrate design, embedded die/capacitor integration, and multi-chip module packaging
  • Hands-on knowledge of assembly processes, qualification methods, DOE and SPC
  • Familiarity with Cu RDL, wafer thinning (Taiko BG), glass carrier bond, and backside metal processes
  • Strong interpersonal, communication, analytical and presentation skills
  • Knowledge of Cu FSM/BGBM technologies

Renesas Electronics Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Renesas Electronics and has not been reviewed or approved by Renesas Electronics.

  • Fair & Transparent Compensation Feedback suggests pay is generally fair-to-good across many roles, with base pay aligned to prevailing market levels in multiple U.S. locations. Engineering and leadership tracks can be competitive on total compensation, reinforcing a sense that pay can meet market expectations in key job families.
  • Healthcare Strength Feedback suggests core medical, dental, and vision coverage is solid and well-regarded by employees. Day-one eligibility in U.S. roles is described, supporting confidence in access and continuity of care.
  • Leave & Time Off Breadth Feedback suggests PTO, paid holidays, sick time, and parental leave provide a comprehensive time-off framework. Company initiatives like Renesas Day and meeting-light Focus Fridays further support time away and balance.

Renesas Electronics Insights

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The Company
HQ: Tokyo
10,040 Employees

What We Do

We're the world's leading semiconductor manufacturer. Our mission is to make our lives easier and a world that's safer, healthier, greener, and smarter.

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