Sr Staff Engineer, RTL Design, IO Subsystem

We are seeking an experienced engineer focused on PCIe & IO Subsystem design for high-performance SOCs.

This role is hybrid, based out of Toronto (ON), Ottawa (ON),  Boston (MA), or Austin (TX)

Responsibilities:

• Design and development of the IO subsystems for a high-performance SoC from scratch, working closely with the Architecture and RTL teams.
• Develop detailed block-level design specifications and plans for a high-performance IO Subsystem.
• Create and implement reusable block-level components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers.
• Develop and optimize the IO subsystem design to ensure functionality and performance are in accordance with architectural specifications
• Evaluate and integrate open-source toolchains into the design flow.
• Collaborate with the design, test, and post-silicon validation teams to ensure high-quality delivery of the IO Subsystems

Experience and Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with 5+ years of experience in IO subsystem design.
• Extensive experience with IO protocols such as PCIe, Ethernet, CXL, and die-to-die protocols (e.g., BoW, UCIe)
• Expertise in designing IO subsystems for CPU- and GPU-based architectures, with a deep understanding of protocols like PCIe, AXI, and CHI.
• Proven experience in tightly coupling hardware with CPUs, ensuring efficient memory access, optimized data paths, and seamless interaction between IO devices and processing cores
• Solid knowledge of PCIe architectural features: ordering rules, non-coherent flows, IO-device memory flows, peer-to-peer communication, bifurcation, and transaction types (posted vs. non-posted).
• Experience with Ethernet protocols, including MAC/PHY design, implementation of packet handling, flow control, and integration of TSN (Time-Sensitive Networking) features. Familiarity with Ethernet-based SoC architectures, low-latency optimizations, and debugging of Ethernet IP in hardware simulation environments using SystemVerilog and UVM for verification.
• Demonstrated problem-solving skills across complex design hierarchies, with the ability to debug and optimize in simulation environments.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.