At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Candidate with knowledge of RTL2GDS Flows
(1) Digital Logic Design
(2) Standard cell circuit design and layout
(3) Spice Circuit simulations
(4) Synthesis with physical layout information
(5) Knowledge of timing (STA), power (UPF, VCD), physical constraints.
(6) Floorplanning, power planning, macro and physical cell placement
(7) Placement of large number of std. cells using tools and scripts for timing/power/area optimization
(8) Clock Tree Synthesis, knowledge of useful skew, H-Tree and Mesh a plus
(9) Routing and DRC cleanup
(10) Signoff Flows including STA, EMIR, DRC/LVS
(11) Knowledge of margining methodologies in advanced nodes
The annual salary range for California is $84,000 to $156,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
