Sr. Principle Design Engineer

Posted 16 Hours Ago
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Austin, TX, USA
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Develop and extend UVM-based functional verification environments, add features, ensure customer configurations pass regressions, support customers, maintain functional and code coverage, and ensure designs meet technical and quality metrics. Focus includes memory controller verification and protocols like DDR/LPDDR/AXI/CHI-E.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This person will work with the existing functional verification environment to add new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage. Additionally, this person will be responsible for ensuring that the design is in line with the technical and quality requirements set for the team – particularly with respect to our quality Metrics.

The position is based in Austin.

Position Requirements:

  • BS/MS - Electrical / Computer Engineering
  • At least 10-12 years of relevant experience including design verification experience.
  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • UVM based functional verification environment development is required.
  • DDR, LPDDR, AXI and/or CHI-E experience is highly desirable.

Memory controller verification experience

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • BS/MS in Electrical or Computer Engineering
  • 10-12 years relevant experience including design verification experience
  • Strong background in functional verification fundamentals, environment planning, test plan generation, and environment development
  • UVM-based functional verification environment development
  • DDR, LPDDR, AXI and/or CHI-E experience
  • Memory controller verification experience

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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