Sr. Principal SI/PI Engineer

Reposted 5 Days Ago
Be an Early Applicant
San Jose, CA, USA
In-Office
179K-332K Annually
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
The Sr Principal SI/PI Engineer role involves optimizing high speed IP products, package design, simulation, and customer support for SI/PI inquiries.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Sr. Principal SI/PI Engineer
This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems. We are looking for a Sr Principal SI/PI Engineer who will be a key contributor to our advanced high speed IP products. This is a hands-on technical position.
Main Job Tasks and Responsibilities:
• Work on test chip package design SI/PI optimization and verification.
• Work on evaluation board design optimization for best SI/PI performance.
• Provide extracted and measured channel models for chip designers in the R&D team.
• Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries.
• Review customer package and board designs and simulation results. Help with providing feedback to customers to ensure best possible performance of our IP in their ASIC.
• Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.
• Help with SI/PI related debug of test chips or customer ASICs in the lab.
Position Requirements:
• M.S. or Ph.D. Electrical Engineering (or similar degree)
• 3+ years of experience preferably working with high speed SerDes and PHYs
• Good understanding of high speed SerDes architecture
• Hands on lab experience with instruments like high speed oscilloscopes, TDRs, VNAs, spectrum analyzers, etc.
• Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave
• Experience with IBIS-AMI model simulations
• Experience with simulation result to lab measurement correlation
• Good understanding of PCB and FCBGA design rules and requirements
• Strong debugging and problem-solving skills
• Excellent communication and presentation skills to effectively communicate with both customers and internal stake holders

The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • M.S. or Ph.D. in Electrical Engineering or similar degree
  • 3+ years of experience with high speed SerDes and PHYs
  • Hands-on lab experience with high speed oscilloscopes, TDRs, VNAs, spectrum analyzers
  • Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave
  • Experience with IBIS-AMI model simulations
  • Strong debugging and problem-solving skills
  • Excellent communication and presentation skills

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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