Sr. Principal Product Engineer

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Homebrook, Grahamdale, MB, CAN
In-Office
144K-267K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Supports Cadence digital implementation and signoff products, troubleshoots customer issues with R&D and release teams, runs design benchmarks, and develops implementation flows and solutions. Provides expertise in ASIC RTL-to-GDSII methodologies, timing closure, PPA optimization, physical design, routing, clock tree synthesis, and silicon signoff for advanced process nodes.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As Product Engineer, you will be a source of technical place and route expertise to Cadence customers and to R&D.

You are a motivated and energetic engineer with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow.
You have proven hands-on experience with timing closure and PPA optimization at 16nm and below nodes.
You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach.
You are an excellent communicator.

Position Responsibilities:
Support Cadence products in the Digital and Signoff team.
Track and debug customer issues and work with R&D and release team on issue resolution.
Run design benchmarks and develop flows and solutions.

Position Requirements:
MS in EE with 2+ years of experience in Digital Implementation, either as a design engineer or as a product engineer
Strong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including clock tree synthesis, routing optimization and silicon signoff.
Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes.
Exposure to, and solid understanding of, hierarchical design methodologies and low power design
Energetic team player with a passion for problem solving
Strong analysis skills with a track record to prove it
Strong communication skills (verbal and written)
Automation skills using Perl, Tcl and shell scripting

The annual salary range for California is $143,500 to $266,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Master’s degree in Electrical Engineering
  • 2+ years of experience in digital implementation as a design engineer or product engineer
  • Deep understanding of ASIC design methodologies and the RTL-to-GDSII flow
  • Hands-on experience with timing closure and PPA optimization at 16nm and below
  • Strong understanding of VLSI physical design and timing analysis
  • Familiarity with clock tree synthesis, routing optimization, and silicon signoff
  • Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 16nm and below
  • Understanding of hierarchical design methodologies and low-power design
  • Automation skills using Perl, Tcl, and shell scripting
  • Strong analytical and problem-solving skills
  • Strong verbal and written communication skills
  • Team-oriented and energetic approach

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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