Sr Principal Design Engineer

Posted 21 Hours Ago
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Bangalore, Bengaluru Urban, Karnataka
Expert/Leader
Cloud • Hardware • Software • Semiconductor
The Role
Join a growing team at Cadence as a Sr Principal Design Engineer, responsible for leading the Design for Test activities for next-gen SoCs. Define DFT architecture, implement verification logic, collaborate with teams, and work on silicon bring up. Ideal candidate has 8-15+ years of experience with key DFT concepts and working knowledge of Verilog coding
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Summary:

Join a growing and dynamic team and help lead the Design for Test activities for next generation of SoCs in advanced technology nodes. As part of the HSV SoC design team, you will be working to define and implement the Design-for-Test architecture and features for SoCs for Palladium® Emulation platforms in advanced technology nodes.

Key Responsibilities

  • Define the DFT Architecture for the next generation SoCs.
  • Implementation & verification including Scan, PMBIST, JTAG and other DFT’s related logic.
  • Define and develop methodology for DFT insertion, pattern development, manufacturing tests, verifications, etc
  • Working closely with cross functional teams to develop and verify DFT’s structures and constraints.
  • Perform RTL and gate level (no-timing and timing) simulations to verify DFT functionality.
  • Work closely with Test Engineering for test program development and Silicon bring up, diagnosis, Yield improvement, etc.
  • Work closely with EDA RnD teams to propose and implement new features.

Requirements:

  • B. Tech /BE/ME/M Tech with 8-15+ years of relevant hands-on experience in Design for Test (DFT).
  • Clear understanding of key DFT concepts like Scan compression, Scan Stitching, fault models (stuck-at, delay tests, IDDQ, Small Delay, etc.), IEEE P1500, MBIST, IEEE 1149.1/6 (Boundary scan), IEEE 1687, etc.
  • Working knowledge of RTL coding in Verilog, Synthesis & STA
  • Experience in at least one scripting language like PERL, Python, TCL, or Shell is preferred.
  • Hands on experience with either Tessent/Modus ATPG tool
  • Proven success in development of complex custom ASIC products in advanced process nodes
  • Hands-on experienced and successful taped out several ASICs.
  • Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.
  • Excellent written and verbal communication skills.

We’re doing work that matters. Help us solve what others can’t.

Top Skills

Perl
Python
Shell
Tcl
Verilog
The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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