Job Description
Key Responsibilities
Hands-on work with Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff, RTL to GDSII.
Lead technical campaigns and strategies in the RTL to GDSII digital implementation space.
Aggressively push Power, Performance, and Area (PPA)
Deliver technical presentations and lead discussions internally and with customers.
Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements with high quality.
Support execution on critical customer flagship product tape outs.
Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows.
Job Requirements
Minimum
MS degree Computer Science/Engineering, Electrical, Engineering, or related field, plus 10+ years industry experience.
Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required.
Prior experience with IC digital implementation flows and backend EDA tools including Synthesis, Place and Route, IR Drop, backend design timing and power closure, RTL to GDSII.
Experience in scripting in Perl/Tcl/Python to automate and implement process improvement is a must.
Floor planning and power planning for System-on-Chip (SoC) designs with low power
MS degree Computer Science/Engineering, Electrical, Engineering, or related field, plus 10+ years industry experience.
Prior experience with IC digital implementation flows and front-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking
Good hands-on experience of Floorplanning, Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suite
Advanced clock tree synthesis techniques including SoC Clock Distribution, Clock Mesh, H-Tree
Multiple design closure including Timing, DRC, LVS, and EMIR preferred.
Experience with advanced technology nodes including Sub 5nm and below.
Develop, debug, and optimize various aspects of design flows for SoC’s to achieve best Power, Performance and Area (PPA)
Strong customer-facing communication and problem-solving skills
Strong personal drive for continuous learning and expanding professional skillsets.
Strong verbal, written, and customer communication skills.
Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus is highly desired.
The annual salary range for California is $148,400 to $275,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Skills Required
- Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field
- 10+ years of industry experience
- Strong knowledge of digital design fundamentals, semiconductor fundamentals, and static timing analysis
- Experience with IC digital implementation flows and backend EDA tools, including synthesis, place and route, IR drop, timing and power closure, and RTL to GDSII
- Experience scripting in Perl, Tcl, or Python for automation and process improvement
- Floorplanning and power planning for low-power SoC designs
- Experience with front-end EDA tools, including synthesis, DFT, and logical equivalence checking
- Hands-on experience with floorplanning, place and route, timing analysis, and signoff
- Advanced clock tree synthesis techniques, including SoC clock distribution, clock mesh, and H-tree
- Experience with advanced technology nodes below 5nm
- Ability to develop, debug, and optimize SoC design flows for power, performance, and area
- Strong customer-facing communication and problem-solving skills
- Strong verbal, written, and customer communication skills
- Experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, or Voltus
- Experience with design closure including timing, DRC, LVS, and EMIR
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
