We’re looking for a senior-level Hardware Design Engineer to take the lead on complex ASIC and FPGA development projects. This role blends architecture design, hands-on implementation, and technical leadership. You’ll collaborate across engineering teams to deliver high-performance, reliable silicon solutions in a flexible hybrid environment.
Responsibilities
- Define HW architecture and evaluate design trade-offs for performance, area, and power.
- Lead RTL development, integration, and verification throughout the design cycle.
- Partner with firmware and verification teams to ensure top-quality silicon delivery.
- Mentor and review junior engineers’ work, promoting best practices and technical excellence.
- Provide design-in and bring-up support, including technical expertise for customer-facing projects.
Qualifications
- Strong command of SystemVerilog for RTL design and digital architecture.
- Experience using simulation tools such as Questa, Incisive, or VCS.
- Skilled in scripting (Python, Perl, Tcl) for automation and workflow optimization.
- Proven experience in ASIC or FPGA design, synthesis, and timing closure.
- Strong analytical thinking and communication skills, with the ability to manage complex priorities.
- 10+ years of relevant experience and a BSEE or MSEE degree.
Preferred / Plus
- Expertise in ASIC synthesis, timing constraints, CDC/RDC methodologies.
- Familiarity with UVM-based verification environments.
- Experience with high-speed memory technologies (HBM, GDDR, LPDDR, DDR).
- Understanding of AMBA AXI or CHI protocols.
Skills Required
- Strong command of SystemVerilog for RTL design and digital architecture
- Experience using simulation tools such as Questa, Incisive, or VCS
- Skilled in scripting for automation (Python, Perl, Tcl)
- Proven experience in ASIC or FPGA design, synthesis, and timing closure
- 10+ years of relevant experience and a BSEE or MSEE degree
What We Do
FortifyIQ engineers certifiable cryptographic IP cores, software libraries, and roots of trust combining traditional algorithms (AES, RSA, ECC, HMAC-SHA2) with post-quantum cryptography (PQC). All hardware IP cores implement RTL-level algorithmic SCA/FIA countermeasures, while software libraries use the same algorithmic protections, delivering high-assurance security with minimal impact on performance, power, or area. Our solutions are foundry- and platform-agnostic, integrating securely across a wide range of devices, from smart cards and IoT nodes to AI accelerators and cloud systems. FortifyIQ validates all designs using proprietary pre- and post-silicon EDA tools, supported by formal proofs, extensive research, and a growing portfolio of patents. FortifyIQ cryptography provides secure boot and post-quantum readiness, with software OTA-updates and asymmetric hardware IP (ECC, RSA, PQC) FOTA-updates, supporting high-assurance embedded, industrial, and cloud systems. By combining rigorous physical attack resilience with near-native efficiency in both hardware and software, FortifyIQ delivers advanced cryptography that is certifiable, reliable, and built to meet the challenges of high-assurance, real-world applications.
