Baya Systems

Sr Formal Verification Engineer

Posted 6 Days Ago

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Bengaluru, Bengaluru Urban, Karnataka

In-Office

Senior level

Semiconductor • Renewable Energy

The Role

As a Senior Formal Verification Engineer, you'll create verification test plans, implement models, optimize design quality, and collaborate on micro-architectural specifications.

Summary Generated by Built In

Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.

Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!

Baya Systems

Senior Formal Verification Engineer

Bengaluru, India (onsite)

Develop detailed formal verification (FV) test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications.

Identify key logic components and critical micro-architectural properties essential for ensuring design correctness.

Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs.

Apply complexity reduction techniques using industry-standard EDA tools or academic formal verification tools to achieve proof convergence or sufficient depth.

Develop and maintain scripts to enhance FV productivity and streamline verification processes.

Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels.

Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback.

Strong proficiency in System Verilog/Verilog.

Good scripting abilities with Python or Perl.

Preferred Experience:

Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold.

Experience with both bug hunting and static proof verification techniques.

Familiarity with automating formal verification workflows within a CI/CD environment.

Compensation:

Salary commensurate with experience
Performance incentives
Comprehensive medical, dental, and vision benefits
401(k) retirement plan
Equity

Top Skills

Eda Tools

Perl

Python

System Verilog

Verilog

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The Company

HQ: Santa Clara, California

84 Employees

What We Do

Baya Systems is driving the next wave of foundational chiplet-based, high-performance, and modular semiconductor systems, with a focus on best-in-class on-chip fabric and communication technologies. By enabling seamless interoperability across a diverse array of industry-standard protocols, Baya Systems empowers best-of-breed compute, communication, and I/O solutions to work together. This approach enhances performance, yield, reusability, composability, development time and cost-efficiency. Named for the Baya bird, renowned for weaving cohesive nests from various materials, Baya Systems embodies this spirit of integration and efficiency. Backed by leading investors Matrix Partners and Intel Capital, Baya Systems is transforming intelligent compute. For more information, visit https://www.bayasystems.com or follow us on Twitter: https://twitter.com/bayasystems.