Sr. Engineer, Analog Mixed-Signal Design

Posted Yesterday
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Hiring Remotely in Berlin, DEU
In-Office or Remote
Senior level
Hardware • Semiconductor • Manufacturing
The Role
Design and verify analog and mixed-signal circuits to meet specifications, contribute to architecture and chip integration, collaborate on layout and DFT/DFM, support bring-up, evaluation and characterization, and work cross-functionally with product, test, and application teams.
Summary Generated by Built In

About SiTime  

SiTime is the Precision Timing company. 


Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.


Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com.


Job Summary


The Sr.Analog Mixed-Signal Design Engineer contributes to building precision timing circuits, leveraging SiTime’s industry-leading MEMS technology.  These products have applications ranging from high-performance Networking and Communications Infrastructure to ultra-low power Mobile platforms, including wearable devices.


Responsibilities:


  • Design analog and mixed-signal circuits meeting architectural requirements and technical specifications
  • Contribute to the architectural definition of the design and chip integration
  • Perform calculations, design and verification simulations to ensure building blocks meet specifications at the schematic level and after post-layout extraction, while fully provisioning for DFT and DFM
  • Work closely with Layout Engineers to validate proper layout, using all best-known methods
  • Document assigned blocks, and hold preliminary and final design review meetings
  • Actively participate in the chip bring upbring-up, evaluation and characterization, with emphasis on owned blocks
  • Work cross-functionally with Product, Characterization, Test, and Application Engineers on issues related to owned circuit blocks
  • Support other projects as needed by management or as business needs change 


Qualifications & Requirements:


  • M.S. in Electrical Engineering or related field with minimum 4 years of related experience, or Ph.D. in Electrical Engineering with minimum 2 years of related experience
  • Excellent academic record with published research projects prototyped and proven in silicon 
  • Detailed knowledge of CMOS circuits and noise analysis
  • Core expertise in one of the following areas:
  • Integer-N and fractional-N PLL (Sigma-Delta and LC)
  • Sigma-Delta ADCs (preferably > 14 ENOB)
  • Temperature sSensor
  • Analog and digital filters
  • Quartz or MEMS oOscillator
  • Sub-threshold circuits
  • Low noise regulator and bandgap
  • High-speed output drivers
  • Knowledge of programming languages: Matlab, VerilogA, Oceanscript,
  • Ability to oversee circuit layout for critical blocks
  • Ability to perform noise analysis 
  • Knowledge of programming languages: MATLAB, VerilogA
  • Proficient in using Cadence analog design tools
  • Ability to oversee circuit layout for critical blocks


Desired Characteristics & Attributes:


  • Passionate, self-starter with a strong commitment to flawless execution
  • Excellent written and verbal communication skills required
  • Ability to work well with others in a fast-paced collaborative team environment

Compensation Range:


At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.


In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals – reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.


SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law.


Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.

  • Innovation on Top – Philosophies of Innovation with Rajesh Vashist
  • Fabrication Knowledge – An Interview with Rajesh Vashist
  • SiTime Corporation – YouTube

#LI-ONSITE

Skills Required

  • M.S. in Electrical Engineering with minimum 4 years related experience, or Ph.D. with minimum 2 years related experience
  • Published research projects prototyped and proven in silicon
  • Detailed knowledge of CMOS circuits and noise analysis
  • Core expertise in one or more: Integer-N and fractional-N PLL (Sigma-Delta and LC), Sigma-Delta ADCs (>14 ENOB), Temperature Sensors, Analog and digital filters, Quartz or MEMS Oscillator, Sub-threshold circuits, Low noise regulator and bandgap, High-speed output drivers
  • Proficient in using Cadence analog design tools
  • Knowledge of programming languages: MATLAB, VerilogA, Oceanscript
  • Ability to oversee circuit layout for critical blocks
  • Ability to perform noise analysis and verification simulations including post-layout extraction
  • Excellent written and verbal communication skills
  • Passionate self-starter with strong commitment to flawless execution
  • Ability to work well with others in a fast-paced collaborative team environment

SiTime Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about SiTime and has not been reviewed or approved by SiTime.

  • Equity Value & Accessibility Feedback suggests equity is a meaningful part of total compensation, with some highlighting the combination of salary, bonus, and stock as a strong point. Company materials emphasize employee equity as a core element of rewards.
  • Wellbeing & Lifestyle Benefits Feedback suggests on-site wellness amenities and daily conveniences (gym, snacks, beverages) support day-to-day wellbeing. The company highlights wellness programs alongside these lifestyle perks.
  • Leave & Time Off Breadth Feedback suggests paid vacation, holidays, sick leave, and volunteer time off are available, reinforcing recharge time. The company emphasizes work-life balance and encourages time to recharge.

SiTime Insights

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The Company
HQ: Santa Clara, CA
465 Employees
Year Founded: 2005

What We Do

SiTime Corporation (Nasdaq: SITM), the market leader in silicon MEMS timing, is an analog and semiconductor company that is revolutionizing the timing market. Our broad portfolio of programmable solutions is available with ultra-fast lead times and offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability.

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